Here is a list of all variables with links to the structures/unions they belong to:
- f -
- f : APB2AVSBUS_AVS_CFG_1_reg_u, BH_PCIE_DWC_PCIE_USP_PF0_HDMA_CAP_HDMA_INT_SETUP_OFF_RDCH_0_reg_u, BH_PCIE_DWC_PCIE_USP_PF0_HDMA_CAP_HDMA_INT_SETUP_OFF_WRCH_0_reg_u, BH_PCIE_DWC_PCIE_USP_PF0_MSI_CAP_HDL_PATH_E982B20F_PCI_MSI_CAP_ID_NEXT_CTRL_REG_reg_u, CHIP_DEBUG_TRACE_CHIP_DEBUG_TRACE_BUFFER_INTR_CNTL_reg_u, CHIP_DEBUG_TRACE_CHIP_DEBUG_TRACE_CLIENT_FILTER_CNT_reg_u, CHIP_DEBUG_TRACE_CHIP_DEBUG_TRACE_IF_CNTL_reg_u, CHIP_DEBUG_TRACE_CHIP_DEBUG_TRACE_REFCLK_COUNTER_CNTL_reg_u, cm2dmAckWire, DW_APB_I2C_IC_CON_reg_u, DW_APB_I2C_IC_RAW_INTR_STAT_reg_u, EFUSE_CNTL_EFUSE_RD_CNTL_reg_u, fd_flags_u, ip_data_reg_u, jtag_instr_u, MSI_CATCHER_STATUS_reg_u, NOC2AXITlb0RegU, NOC2AXITlb1RegU, NOC2AXITlb2RegU, NOC2AXITlb3RegU, PCIE_SII_APP_PCIE_CTL_reg_u, PCIE_SII_LTSSM_STATE_reg_u, PCIE_SII_NOC_TLB_DATA_reg_u, pd_ip_cfg0_u, PLL_CNTL_PLL_CNTL_0_reg_u, PLL_CNTL_PLL_CNTL_1_reg_u, PLL_CNTL_PLL_CNTL_2_reg_u, PLL_CNTL_PLL_CNTL_3_reg_u, PLL_CNTL_PLL_CNTL_4_reg_u, PLL_CNTL_PLL_CNTL_5_reg_u, PLL_CNTL_USE_POSTDIV_reg_u, PLL_CNTL_WRAPPER_CLOCK_WAVE_CNTL_reg_u, PLL_CNTL_WRAPPER_PLL_LOCK_reg_u, PMM_BLOCK_PMM_CTRL_reg_u, PMM_BLOCK_PMM_MESSAGE_reg_u, pvt_cntl_clk_synth_reg_u, pvt_cntl_irq_en_reg_u, pvt_cntl_sdif_reg_u, pvt_cntl_sdif_status_reg_u, pvt_cntl_ts_pd_irq_enable_reg_u, pvt_cntl_ts_pd_sdif_data_reg_u, pvt_cntl_vm_alarma_cfg_reg_u, pvt_cntl_vm_alarmb_cfg_reg_u, pvt_cntl_vm_irq_enable_reg_u, RESET_UNIT_ARC_MISC_CNTL_reg_u, RESET_UNIT_CATMON_THERM_TRIP_CNTL_reg_u, RESET_UNIT_CHIP_DEBUG_TRACE_IF_CNTL_reg_u, RESET_UNIT_DDR_RESET_reg_u, RESET_UNIT_ETH_RESET_reg_u, RESET_UNIT_GLOBAL_RESET_reg_u, RESET_UNIT_L2CPU_RESET_reg_u, RESET_UNIT_PCIE_MISC_CNTL3_reg_u, RESET_UNIT_TENSIX_RESET_reg_u, RESET_UNIT_UART_CNTL_reg_u, security_fd_flags_u, STATUS_BOOT_STATUS0_reg_u, STATUS_ERROR_STATUS0_reg_u, ts_ip_cfg0_u, tt_bh_pll_cntl_0_reg, tt_bh_pll_cntl_1_reg, tt_bh_pll_cntl_2_reg, tt_bh_pll_cntl_3_reg, tt_bh_pll_cntl_5_reg, tt_bh_pll_cntl_wrapper_lock_reg, tt_bh_pll_use_postdiv_reg, UART_ADDRESS_BLOCK_IIR_reg_u, UART_ADDRESS_BLOCK_LCR_reg_u, UART_ADDRESS_BLOCK_LSR_reg_u
- failed : gddr_bist_info
- fan_speed : bh_chip_data
- fan_speed_forced : bh_chip_data
- fbdiv : PLL_CNTL_PLL_CNTL_1_reg_t, tt_bh_pll_cntl_1_fields
- fd_crc : tt_boot_fs_fd
- fd_flags_rsvd : fd_flags
- fe : UART_ADDRESS_BLOCK_LSR_reg_t
- feature_bits : gddr_params_table_t
- fifose : UART_ADDRESS_BLOCK_IIR_reg_t
- flag0 : PMM_BLOCK_PMM_MESSAGE_reg_t
- flag1 : PMM_BLOCK_PMM_MESSAGE_reg_t
- flag2 : PMM_BLOCK_PMM_MESSAGE_reg_t
- flag3 : PMM_BLOCK_PMM_MESSAGE_reg_t
- flags : occp_cmd_header, tt_boot_fs_fd
- flash : bh_chip_config, bh_fwtable_config
- flash_dev : flash_stm32_wrapper_config
- flash_info_table : bh_fwtable_data
- flash_lock : request
- flash_unlock : request
- fmax : AiclkPPM
- fmin : AiclkPPM
- fmin_value : characterisation_submsg_data
- force_aiclk : request
- force_fan_speed : request
- force_slave_resync_operation : APB2AVSBUS_AVS_CFG_1_reg_t
- force_vdd : request
- forced_freq : AiclkPPM, force_aiclk_rqst
- forced_voltage : force_vdd_rqst, VoltageArbiter
- func : cycle_cnt
- future_use : power_setting_rqst
- fw_id : STATUS_BOOT_STATUS0_reg_t
- fw_table : bh_fwtable_data
1.14.0