gddr_telemetry_table.h

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/*
 * Copyright (c) 2024 Tenstorrent AI ULC
 * SPDX-License-Identifier: Apache-2.0
 */
 
#ifndef GDDR_TELEMETRY_TABLE_H
#define GDDR_TELEMETRY_TABLE_H
 
/* ***************************************
 *      THIS FILE IS AUTO GENERATED
 * ***************************************
 * *** DO NOT EDIT THIS FILE MANUALLY ****
 * To edit, modify
 * gddr_telemetry_table.yaml and run make.
 * ***************************************
 */
#include <stdint.h>
 
#define GDDR_TELEMETRY_TABLE_T_VERSION (0x00000003)
 
typedef struct {
        uint32_t telemetry_table_version;
        /* To be incremented if the fields change functionality, size or order. */
        uint16_t dram_temperature_top;
        /* Temperature in Celsius of the top DRAM die */
        uint16_t dram_temperature_bottom;
        /* Temperature in Celsius of the bottom DRAM die */
        uint16_t dram_speed;
        /* Speed in Mbps */
        uint8_t training_complete;
        /* 0 = Incomplete, 1 = Complete */
        uint8_t gddr_error;
        /* 0 = No error, 1 = Error. Will be set on any fatal error to FW (e.g. training fails). */
        uint16_t mrisc_fw_version_major;
        /* MRISC Major Firmware version number */
        uint16_t mrisc_fw_version_minor;
        /* MRISC Minor Firmware version number */
        uint32_t dram_vendor;
        /* 0 = Unknown, 1 = Samsung_C_Die, 2 = Micron_C_Die, 3 = Micron_E_Die */
        uint8_t corr_edc_rd_errors;
        /* Saturates at 255. Number of cumulative corrected EDC errors on read since reset. */
        uint8_t corr_edc_wr_errors;
        /* Saturates at 255. Number of cumulative corrected EDC errors on write since reset. */
        uint8_t uncorr_edc_rd_error;
        /* 1 if any uncorrected EDC errors on read since reset. */
        uint8_t uncorr_edc_wr_error;
        /* 1 if any uncorrected EDC errors on write since reset. */
        uint8_t ca_vrefc_offset;
        /* Applied CA VREFC offset as 4-bit two's-complement MR10 OP[3:0] code. */
        uint8_t ca_termination_offset;
        /* Applied CA termination offset (MR3, 0-3). */
        uint8_t ca_settings_source;
        /*
         * Where the applied CA settings came from. 0 = FW default LUT,
         * 1 = params table (SMC-seeded), 2 = runtime CA sweep.
         */
        uint8_t ca_settings_changed;
        /*
         * 1 = Applied CA settings differ from the seeded/default values
         * (SMC should latch them to flash).
         */
        uint8_t ca_margin_check_status;
        /* Post-training CA margin check result. 0 = not run, 1 = pass, 2 = fail. */
        uint8_t ca_sweep_status;
        /*
         * Runtime CA sweep result. 0 = not run, 1 = completed with passing window,
         * 2 = completed with no passing window.
         */
        int8_t ca_window_min_offset;
        /*
         * Lowest passing CA VREFC offset (signed) observed by the margin check or sweep.
         * 0x7F = invalid/not measured.
         */
        int8_t ca_window_max_offset;
        /*
         * Highest passing CA VREFC offset (signed) observed by the margin check or sweep.
         * 0x7F = invalid/not measured.
         */
        uint8_t ca_ocd_pulldown_offset;
        /*
         * Applied CA driver strength as 3-bit OCD pulldown offset code
         * (0-3 = 0..+3, 4-7 = -4..-1).
         */
        uint8_t ca_reserved0;
        /* Reserved, reads 0. */
        uint8_t ca_reserved1;
        /* Reserved, reads 0. */
        uint8_t ca_reserved2;
        /* Reserved, reads 0. */
} gddr_telemetry_table_t;
 
#endif