msgqueue.h

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/*
 * Copyright (c) 2024 Tenstorrent AI ULC
 *
 * SPDX-License-Identifier: Apache-2.0
 */
 
#ifndef TENSTORRENT_MSGQUEUE_H_
#define TENSTORRENT_MSGQUEUE_H_
 
#include <stdint.h>
 
#include <zephyr/sys/iterable_sections.h>
 
#define NUM_MSG_QUEUES         4
#define MSG_QUEUE_SIZE         4
#define MSG_QUEUE_POINTER_WRAP (2 * MSG_QUEUE_SIZE)
#define REQUEST_MSG_LEN        8
#define RESPONSE_MSG_LEN       8
 
#define MSG_TYPE_INDEX 0
#define MSG_TYPE_MASK  0xFF
#define MSG_TYPE_SHIFT 0
 
#define MESSAGE_QUEUE_STATUS_MESSAGE_RECOGNIZED 0xff
#define MESSAGE_QUEUE_STATUS_SCRATCH_ONLY       0xfe
 
#ifdef __cplusplus
extern "C" {
#endif
 
struct message_queue_header {
        /* 16B for CPU writes, ARC reads */
        uint32_t request_queue_wptr;
        uint32_t response_queue_rptr;
        uint32_t unused_1;
        uint32_t unused_2;
 
        /* 16B for ARC writes, CPU reads */
        uint32_t request_queue_rptr;
        uint32_t response_queue_wptr;
        uint32_t last_serial;
        uint32_t unused_3;
};



enum counter_cmd {
        COUNTER_CMD_GET,
        COUNTER_CMD_CLEAR,
        COUNTER_CMD_FREEZE,
};

enum counter_bank {
        COUNTER_BANK_THROTTLERS,
};

struct counter_rqst {
        uint8_t command_code;

        uint8_t pad[3];

        uint8_t command;

        uint8_t counter_bank;

        uint8_t bank_index;

        uint8_t reserved[1];

        uint16_t mask;
};

struct force_fan_speed_rqst {
        uint8_t command_code;

        uint8_t pad[3];

        uint32_t raw_speed;
};

struct aiclk_set_speed_rqst {
        uint8_t command_code;

        uint8_t pad[3];
};

struct aisweep_rqst {
        uint8_t command_code;

        uint8_t pad[3];

        uint32_t sweep_low;

        uint32_t sweep_high;
};

struct force_aiclk_rqst {
        uint8_t command_code;

        uint8_t pad[3];

        uint32_t forced_freq;
};

struct get_aiclk_rqst {
        uint8_t command_code;
};

struct power_setting_rqst {
        uint8_t command_code;

        uint8_t power_flags_valid: 4;

        uint8_t power_settings_valid: 4;

        struct {
                uint16_t max_ai_clk: 1;

                uint16_t mrisc_phy_power: 1;

                uint16_t tensix_enable: 1;

                uint16_t l2cpu_enable: 1;

                uint16_t future_use: 11;

                uint16_t reserved: 1;
        } power_flags_bitfield;
 
        struct {
                uint16_t future_use[14];
        } power_settings_array;
};

struct set_voltage_rqst {
        uint8_t command_code;

        uint8_t pad[3];

        uint32_t slave_addr;

        uint32_t voltage_in_mv;
};

struct get_voltage_rqst {
        uint8_t command_code;

        uint8_t pad[3];

        uint32_t slave_addr;
};

struct force_vdd_rqst {
        uint8_t command_code;

        uint8_t pad[3];

        uint32_t forced_voltage;
};

struct switch_vout_control_rqst {
        uint8_t command_code;

        uint8_t pad[3];

        uint32_t source;
};

struct switch_clk_scheme_rqst {
        uint8_t command_code;

        uint8_t pad[3];

        uint32_t scheme;
};

struct get_freq_curve_from_voltage_rqst {
        uint8_t command_code;

        uint8_t pad[3];

        uint32_t input_voltage_mv;
};

struct get_voltage_curve_from_freq_rqst {
        uint8_t command_code;

        uint8_t pad[3];

        uint32_t input_freq_mhz;
};

struct debug_noc_translation_rqst {
        uint8_t command_code;

        uint8_t enable_translation: 1;

        uint8_t pcie_instance: 1;

        uint8_t pcie_instance_override: 1;

        uint16_t bad_tensix_cols;

        uint8_t bad_gddr;

        uint8_t skip_eth_low;

        uint8_t skip_eth_hi;
};

struct dmc_ping_rqst {
        uint8_t command_code;

        uint8_t pad[3];

        bool legacy_ping;
};

struct send_pcie_msi_rqst {
        uint8_t command_code;

        uint8_t pcie_inst: 1;

        uint8_t pad[2];

        uint32_t vector_id;
};

struct i2c_message_rqst {
        uint8_t command_code;

        uint8_t i2c_mst_id;

        uint8_t i2c_slave_address;

        uint8_t num_write_bytes;

        uint8_t num_read_bytes;

        uint8_t pad[3];

        uint8_t write_data[24];
};

struct led_blink_rqst {
        uint8_t command_code;

        uint8_t pad[3];

        uint8_t is_blinking: 1;
};

struct test_rqst {
        uint8_t command_code;

        uint8_t pad[3];

        uint32_t test_value;
};

struct pcie_dma_transfer_rqst {
        uint8_t command_code;

        uint8_t completion_data;

        uint8_t pad[2];

        uint32_t transfer_size_bytes;

        uint64_t chip_addr;

        uint64_t host_addr;

        uint64_t msi_completion_addr;
};

struct gddr_reset_rqst {
        uint8_t command_code;

        uint8_t pad[3];

        uint32_t gddr_inst;
};

enum gddr_reset_err {
        GDDR_RESET_ERR_INVALID_INST = 1,
        GDDR_RESET_ERR_HARVESTED = 2,
        GDDR_RESET_ERR_MASKED = 3,
        GDDR_RESET_ERR_TRAINING = 4,
        GDDR_RESET_ERR_BIST = 5,
        GDDR_RESET_ERR_POWERDOWN = 6,
};

struct trigger_reset_rqst {
        uint8_t command_code;

        uint8_t pad[3];

        uint32_t reset_level;
};

struct asic_state_rqst {
        uint8_t command_code;
};

struct read_ts_rqst {
        uint8_t command_code;

        uint8_t pad[3];

        uint32_t sensor_id;
};

struct eeprom_rqst {
        uint8_t command_code;

        uint8_t buffer_mem_type;

        uint8_t pad[2];

        uint32_t spi_address;

        uint32_t num_bytes;

        uint32_t csm_addr;
};

struct read_pd_rqst {
        uint8_t command_code;

        uint8_t pad[3];

        uint32_t delay_chain;

        uint32_t sensor_id;
};

struct read_vm_rqst {
        uint8_t command_code;

        uint8_t pad[3];

        uint32_t sensor_id;
};

struct set_tdp_limit_rqst {
        uint8_t command_code;

        uint8_t pad[3];

        uint32_t tdp_limit;

        uint8_t restore_default: 1;
};

struct report_scratch_only_rqst {
        uint8_t command_code;
};

struct set_asic_host_fmax_rqst {
        uint8_t command_code;
        uint8_t pad[3];
        uint32_t asic_fmax;
        uint8_t restore_default: 1;
};

struct reinit_tensix_rqst {
        uint8_t command_code;
};

struct toggle_tensix_reset_rqst {
        uint8_t command_code;
};

struct flash_unlock_rqst {
        uint8_t command_code;

        uint8_t pad[3];
};

struct set_wdt_timeout_rqst {
        uint8_t command_code;

        uint8_t pad[3];

        uint32_t timeout_ms;
};

struct flash_lock_rqst {
        uint8_t command_code;

        uint8_t pad[3];
};

struct confirm_flashed_spi_rqst {
        uint8_t command_code;

        uint8_t pad[3];

        uint32_t challenge_data;
};

union request {
        uint32_t data[REQUEST_MSG_LEN];

        uint8_t command_code;

        struct force_fan_speed_rqst force_fan_speed;

        struct aiclk_set_speed_rqst aiclk_set_speed;

        struct aisweep_rqst aisweep;

        struct force_aiclk_rqst force_aiclk;

        struct get_aiclk_rqst get_aiclk;

        struct power_setting_rqst power_setting;

        struct set_voltage_rqst set_voltage;

        struct get_voltage_rqst get_voltage;

        struct force_vdd_rqst force_vdd;

        struct switch_vout_control_rqst switch_vout_control;

        struct switch_clk_scheme_rqst switch_clk_scheme;

        struct get_freq_curve_from_voltage_rqst get_freq_curve_from_voltage;

        struct get_voltage_curve_from_freq_rqst get_voltage_curve_from_freq;

        struct debug_noc_translation_rqst debug_noc_translation;

        struct dmc_ping_rqst dmc_ping;

        struct send_pcie_msi_rqst send_pci_msi;

        struct i2c_message_rqst i2c_message;

        struct led_blink_rqst blink;

        struct test_rqst test;

        struct pcie_dma_transfer_rqst pcie_dma_transfer;

        struct asic_state_rqst asic_state;

        struct trigger_reset_rqst trigger_reset;

        struct gddr_reset_rqst gddr_reset;

        struct read_ts_rqst read_ts;

        struct read_vm_rqst read_vm;

        struct read_pd_rqst read_pd;

        struct set_tdp_limit_rqst set_tdp_limit;

        struct eeprom_rqst eeprom;

        struct set_asic_host_fmax_rqst set_asic_host_fmax;

        struct report_scratch_only_rqst report_scratch_only;

        struct counter_rqst counter;

        struct set_wdt_timeout_rqst set_wdt_timeout;

        struct flash_unlock_rqst flash_unlock;

        struct flash_lock_rqst flash_lock;

        struct confirm_flashed_spi_rqst confirm_flashed_spi;
};


 
struct response {
        uint32_t data[RESPONSE_MSG_LEN];
};
 
typedef uint8_t (*msgqueue_request_handler_t)(const union request *req, struct response *rsp);
 
struct msgqueue_handler {
        uint32_t msg_type;
        msgqueue_request_handler_t handler;
};
 
#define REGISTER_MESSAGE(msg, func)                                                                \
        const STRUCT_SECTION_ITERABLE(msgqueue_handler, registration_for_##msg) = {                \
                .msg_type = msg,                                                                   \
                .handler = func,                                                                   \
        }
 
void process_message_queues(void);
void msgqueue_register_handler(uint32_t msg_code, msgqueue_request_handler_t handler);
 
int msgqueue_request_push(uint32_t msgqueue_id, const union request *request);
int msgqueue_request_pop(uint32_t msgqueue_id, union request *request);
int msgqueue_response_push(uint32_t msgqueue_id, const struct response *response);
int msgqueue_response_pop(uint32_t msgqueue_id, struct response *response);
void init_msgqueue(void);
 
#ifdef __cplusplus
}
#endif
 
#endif