types_generated.h

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// automatically generated by the FlatBuffers compiler, do not modify
 
 
#ifndef FLATBUFFERS_GENERATED_TYPES_TT_TARGET_H_
#define FLATBUFFERS_GENERATED_TYPES_TT_TARGET_H_
 
#include "flatbuffers/flatbuffers.h"
 
// Ensure the included flatbuffers.h is the same version as when this file was
// generated, otherwise it may not be compatible.
static_assert(FLATBUFFERS_VERSION_MAJOR == 24 &&
              FLATBUFFERS_VERSION_MINOR == 3 &&
              FLATBUFFERS_VERSION_REVISION == 25,
             "Non-compatible flatbuffers version included");
 
namespace tt {
namespace target {
 
struct Dim2d;
 
struct Dim2dRange;
 
struct ChipDesc;
struct ChipDescBuilder;
 
struct ChipCoord;
 
struct ChipChannel;
 
struct ChipPhysicalCores;
struct ChipPhysicalCoresBuilder;
 
struct CPUDesc;
struct CPUDescBuilder;
 
struct SystemDesc;
struct SystemDescBuilder;
 
struct DeviceRef;
struct DeviceRefBuilder;
 
struct EventRef;
struct EventRefBuilder;
 
struct DynamicLib;
struct DynamicLibBuilder;
 
enum class Arch : uint32_t {
  Grayskull = 0,
  Wormhole_b0 = 1,
  Blackhole = 2,
  MIN = Grayskull,
  MAX = Blackhole
};
 
inline const Arch (&EnumValuesArch())[3] {
  static const Arch values[] = {
    Arch::Grayskull,
    Arch::Wormhole_b0,
    Arch::Blackhole
  };
  return values;
}
 
inline const char * const *EnumNamesArch() {
  static const char * const names[4] = {
    "Grayskull",
    "Wormhole_b0",
    "Blackhole",
    nullptr
  };
  return names;
}
 
inline const char *EnumNameArch(Arch e) {
  if (::flatbuffers::IsOutRange(e, Arch::Grayskull, Arch::Blackhole)) return "";
  const size_t index = static_cast<size_t>(e);
  return EnumNamesArch()[index];
}
 
enum class DataType : uint16_t {
  Float32 = 0,
  Float16 = 1,
  BFloat16 = 2,
  BFP_Float8 = 3,
  BFP_BFloat8 = 4,
  BFP_Float4 = 5,
  BFP_BFloat4 = 6,
  BFP_Float2 = 7,
  BFP_BFloat2 = 8,
  UInt32 = 9,
  UInt16 = 10,
  UInt8 = 11,
  MIN = Float32,
  MAX = UInt8
};
 
inline const DataType (&EnumValuesDataType())[12] {
  static const DataType values[] = {
    DataType::Float32,
    DataType::Float16,
    DataType::BFloat16,
    DataType::BFP_Float8,
    DataType::BFP_BFloat8,
    DataType::BFP_Float4,
    DataType::BFP_BFloat4,
    DataType::BFP_Float2,
    DataType::BFP_BFloat2,
    DataType::UInt32,
    DataType::UInt16,
    DataType::UInt8
  };
  return values;
}
 
inline const char * const *EnumNamesDataType() {
  static const char * const names[13] = {
    "Float32",
    "Float16",
    "BFloat16",
    "BFP_Float8",
    "BFP_BFloat8",
    "BFP_Float4",
    "BFP_BFloat4",
    "BFP_Float2",
    "BFP_BFloat2",
    "UInt32",
    "UInt16",
    "UInt8",
    nullptr
  };
  return names;
}
 
inline const char *EnumNameDataType(DataType e) {
  if (::flatbuffers::IsOutRange(e, DataType::Float32, DataType::UInt8)) return "";
  const size_t index = static_cast<size_t>(e);
  return EnumNamesDataType()[index];
}
 
enum class OOBVal : uint16_t {
  Undef = 0,
  Zero = 1,
  One = 2,
  Inf = 3,
  NegInf = 4,
  MIN = Undef,
  MAX = NegInf
};
 
inline const OOBVal (&EnumValuesOOBVal())[5] {
  static const OOBVal values[] = {
    OOBVal::Undef,
    OOBVal::Zero,
    OOBVal::One,
    OOBVal::Inf,
    OOBVal::NegInf
  };
  return values;
}
 
inline const char * const *EnumNamesOOBVal() {
  static const char * const names[6] = {
    "Undef",
    "Zero",
    "One",
    "Inf",
    "NegInf",
    nullptr
  };
  return names;
}
 
inline const char *EnumNameOOBVal(OOBVal e) {
  if (::flatbuffers::IsOutRange(e, OOBVal::Undef, OOBVal::NegInf)) return "";
  const size_t index = static_cast<size_t>(e);
  return EnumNamesOOBVal()[index];
}
 
enum class MemorySpace : uint16_t {
  System = 0,
  SystemMMIO = 1,
  DeviceDRAM = 2,
  DeviceL1 = 3,
  MIN = System,
  MAX = DeviceL1
};
 
inline const MemorySpace (&EnumValuesMemorySpace())[4] {
  static const MemorySpace values[] = {
    MemorySpace::System,
    MemorySpace::SystemMMIO,
    MemorySpace::DeviceDRAM,
    MemorySpace::DeviceL1
  };
  return values;
}
 
inline const char * const *EnumNamesMemorySpace() {
  static const char * const names[5] = {
    "System",
    "SystemMMIO",
    "DeviceDRAM",
    "DeviceL1",
    nullptr
  };
  return names;
}
 
inline const char *EnumNameMemorySpace(MemorySpace e) {
  if (::flatbuffers::IsOutRange(e, MemorySpace::System, MemorySpace::DeviceL1)) return "";
  const size_t index = static_cast<size_t>(e);
  return EnumNamesMemorySpace()[index];
}
 
enum class ChipCapability : uint32_t {
  PCIE = 1,
  HostMMIO = 2,
  NONE = 0,
  ANY = 3
};
FLATBUFFERS_DEFINE_BITMASK_OPERATORS(ChipCapability, uint32_t)
 
inline const ChipCapability (&EnumValuesChipCapability())[2] {
  static const ChipCapability values[] = {
    ChipCapability::PCIE,
    ChipCapability::HostMMIO
  };
  return values;
}
 
inline const char * const *EnumNamesChipCapability() {
  static const char * const names[3] = {
    "PCIE",
    "HostMMIO",
    nullptr
  };
  return names;
}
 
inline const char *EnumNameChipCapability(ChipCapability e) {
  if (::flatbuffers::IsOutRange(e, ChipCapability::PCIE, ChipCapability::HostMMIO)) return "";
  const size_t index = static_cast<size_t>(e) - static_cast<size_t>(ChipCapability::PCIE);
  return EnumNamesChipCapability()[index];
}
 
enum class TensorLayout : uint16_t {
  RowMajor = 0,
  Tile = 1,
  Invalid = 2,
  MIN = RowMajor,
  MAX = Invalid
};
 
inline const TensorLayout (&EnumValuesTensorLayout())[3] {
  static const TensorLayout values[] = {
    TensorLayout::RowMajor,
    TensorLayout::Tile,
    TensorLayout::Invalid
  };
  return values;
}
 
inline const char * const *EnumNamesTensorLayout() {
  static const char * const names[4] = {
    "RowMajor",
    "Tile",
    "Invalid",
    nullptr
  };
  return names;
}
 
inline const char *EnumNameTensorLayout(TensorLayout e) {
  if (::flatbuffers::IsOutRange(e, TensorLayout::RowMajor, TensorLayout::Invalid)) return "";
  const size_t index = static_cast<size_t>(e);
  return EnumNamesTensorLayout()[index];
}
 
enum class BufferType : uint16_t {
  DRAM = 0,
  L1 = 1,
  SystemMemory = 2,
  L1Small = 3,
  Trace = 4,
  MIN = DRAM,
  MAX = Trace
};
 
inline const BufferType (&EnumValuesBufferType())[5] {
  static const BufferType values[] = {
    BufferType::DRAM,
    BufferType::L1,
    BufferType::SystemMemory,
    BufferType::L1Small,
    BufferType::Trace
  };
  return values;
}
 
inline const char * const *EnumNamesBufferType() {
  static const char * const names[6] = {
    "DRAM",
    "L1",
    "SystemMemory",
    "L1Small",
    "Trace",
    nullptr
  };
  return names;
}
 
inline const char *EnumNameBufferType(BufferType e) {
  if (::flatbuffers::IsOutRange(e, BufferType::DRAM, BufferType::Trace)) return "";
  const size_t index = static_cast<size_t>(e);
  return EnumNamesBufferType()[index];
}
 
enum class CPURole : uint8_t {
  Host = 0,
  Device = 1,
  MIN = Host,
  MAX = Device
};
 
inline const CPURole (&EnumValuesCPURole())[2] {
  static const CPURole values[] = {
    CPURole::Host,
    CPURole::Device
  };
  return values;
}
 
inline const char * const *EnumNamesCPURole() {
  static const char * const names[3] = {
    "Host",
    "Device",
    nullptr
  };
  return names;
}
 
inline const char *EnumNameCPURole(CPURole e) {
  if (::flatbuffers::IsOutRange(e, CPURole::Host, CPURole::Device)) return "";
  const size_t index = static_cast<size_t>(e);
  return EnumNamesCPURole()[index];
}
 
enum class MathFidelity : uint8_t {
  LoFi = 0,
  HiFi2 = 2,
  HiFi3 = 3,
  HiFi4 = 4,
  MIN = LoFi,
  MAX = HiFi4
};
 
inline const MathFidelity (&EnumValuesMathFidelity())[4] {
  static const MathFidelity values[] = {
    MathFidelity::LoFi,
    MathFidelity::HiFi2,
    MathFidelity::HiFi3,
    MathFidelity::HiFi4
  };
  return values;
}
 
inline const char * const *EnumNamesMathFidelity() {
  static const char * const names[6] = {
    "LoFi",
    "",
    "HiFi2",
    "HiFi3",
    "HiFi4",
    nullptr
  };
  return names;
}
 
inline const char *EnumNameMathFidelity(MathFidelity e) {
  if (::flatbuffers::IsOutRange(e, MathFidelity::LoFi, MathFidelity::HiFi4)) return "";
  const size_t index = static_cast<size_t>(e);
  return EnumNamesMathFidelity()[index];
}
 
FLATBUFFERS_MANUALLY_ALIGNED_STRUCT(4) Dim2d FLATBUFFERS_FINAL_CLASS {
 private:
  int32_t y_;
  int32_t x_;
 
 public:
  struct Traits;
  Dim2d()
      : y_(0),
        x_(0) {
  }
  Dim2d(int32_t _y, int32_t _x)
      : y_(::flatbuffers::EndianScalar(_y)),
        x_(::flatbuffers::EndianScalar(_x)) {
  }
  int32_t y() const {
    return ::flatbuffers::EndianScalar(y_);
  }
  int32_t x() const {
    return ::flatbuffers::EndianScalar(x_);
  }
};
FLATBUFFERS_STRUCT_END(Dim2d, 8);
 
struct Dim2d::Traits {
  using type = Dim2d;
};
 
FLATBUFFERS_MANUALLY_ALIGNED_STRUCT(4) Dim2dRange FLATBUFFERS_FINAL_CLASS {
 private:
  tt::target::Dim2d loc_;
  tt::target::Dim2d size_;
 
 public:
  struct Traits;
  Dim2dRange()
      : loc_(),
        size_() {
  }
  Dim2dRange(const tt::target::Dim2d &_loc, const tt::target::Dim2d &_size)
      : loc_(_loc),
        size_(_size) {
  }
  const tt::target::Dim2d &loc() const {
    return loc_;
  }
  const tt::target::Dim2d &size() const {
    return size_;
  }
};
FLATBUFFERS_STRUCT_END(Dim2dRange, 16);
 
struct Dim2dRange::Traits {
  using type = Dim2dRange;
};
 
FLATBUFFERS_MANUALLY_ALIGNED_STRUCT(4) ChipCoord FLATBUFFERS_FINAL_CLASS {
 private:
  uint32_t rack_;
  uint32_t shelf_;
  uint32_t y_;
  uint32_t x_;
 
 public:
  struct Traits;
  ChipCoord()
      : rack_(0),
        shelf_(0),
        y_(0),
        x_(0) {
  }
  ChipCoord(uint32_t _rack, uint32_t _shelf, uint32_t _y, uint32_t _x)
      : rack_(::flatbuffers::EndianScalar(_rack)),
        shelf_(::flatbuffers::EndianScalar(_shelf)),
        y_(::flatbuffers::EndianScalar(_y)),
        x_(::flatbuffers::EndianScalar(_x)) {
  }
  uint32_t rack() const {
    return ::flatbuffers::EndianScalar(rack_);
  }
  uint32_t shelf() const {
    return ::flatbuffers::EndianScalar(shelf_);
  }
  uint32_t y() const {
    return ::flatbuffers::EndianScalar(y_);
  }
  uint32_t x() const {
    return ::flatbuffers::EndianScalar(x_);
  }
};
FLATBUFFERS_STRUCT_END(ChipCoord, 16);
 
struct ChipCoord::Traits {
  using type = ChipCoord;
};
 
FLATBUFFERS_MANUALLY_ALIGNED_STRUCT(4) ChipChannel FLATBUFFERS_FINAL_CLASS {
 private:
  uint32_t device_id0_;
  tt::target::Dim2d ethernet_core_coord0_;
  uint32_t device_id1_;
  tt::target::Dim2d ethernet_core_coord1_;
 
 public:
  struct Traits;
  ChipChannel()
      : device_id0_(0),
        ethernet_core_coord0_(),
        device_id1_(0),
        ethernet_core_coord1_() {
  }
  ChipChannel(uint32_t _device_id0, const tt::target::Dim2d &_ethernet_core_coord0, uint32_t _device_id1, const tt::target::Dim2d &_ethernet_core_coord1)
      : device_id0_(::flatbuffers::EndianScalar(_device_id0)),
        ethernet_core_coord0_(_ethernet_core_coord0),
        device_id1_(::flatbuffers::EndianScalar(_device_id1)),
        ethernet_core_coord1_(_ethernet_core_coord1) {
  }
  uint32_t device_id0() const {
    return ::flatbuffers::EndianScalar(device_id0_);
  }
  const tt::target::Dim2d &ethernet_core_coord0() const {
    return ethernet_core_coord0_;
  }
  uint32_t device_id1() const {
    return ::flatbuffers::EndianScalar(device_id1_);
  }
  const tt::target::Dim2d &ethernet_core_coord1() const {
    return ethernet_core_coord1_;
  }
};
FLATBUFFERS_STRUCT_END(ChipChannel, 24);
 
struct ChipChannel::Traits {
  using type = ChipChannel;
};
 
struct ChipDesc FLATBUFFERS_FINAL_CLASS : private ::flatbuffers::Table {
  typedef ChipDescBuilder Builder;
  struct Traits;
  enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE {
    VT_ARCH = 4,
    VT_GRID_SIZE = 6,
    VT_L1_SIZE = 8,
    VT_NUM_DRAM_CHANNELS = 10,
    VT_DRAM_CHANNEL_SIZE = 12,
    VT_NOC_L1_ADDRESS_ALIGN_BYTES = 14,
    VT_PCIE_ADDRESS_ALIGN_BYTES = 16,
    VT_NOC_DRAM_ADDRESS_ALIGN_BYTES = 18,
    VT_L1_UNRESERVED_BASE = 20,
    VT_ERISC_L1_UNRESERVED_BASE = 22,
    VT_DRAM_UNRESERVED_BASE = 24,
    VT_DRAM_UNRESERVED_END = 26,
    VT_PHYSICAL_CORES = 28,
    VT_SUPPORTED_DATA_TYPES = 30,
    VT_SUPPORTED_TILE_SIZES = 32,
    VT_NUM_CBS = 34
  };
  tt::target::Arch arch() const {
    return static_cast<tt::target::Arch>(GetField<uint32_t>(VT_ARCH, 0));
  }
  const tt::target::Dim2d *grid_size() const {
    return GetStruct<const tt::target::Dim2d *>(VT_GRID_SIZE);
  }
  uint64_t l1_size() const {
    return GetField<uint64_t>(VT_L1_SIZE, 0);
  }
  uint32_t num_dram_channels() const {
    return GetField<uint32_t>(VT_NUM_DRAM_CHANNELS, 0);
  }
  uint64_t dram_channel_size() const {
    return GetField<uint64_t>(VT_DRAM_CHANNEL_SIZE, 0);
  }
  uint32_t noc_l1_address_align_bytes() const {
    return GetField<uint32_t>(VT_NOC_L1_ADDRESS_ALIGN_BYTES, 0);
  }
  uint32_t pcie_address_align_bytes() const {
    return GetField<uint32_t>(VT_PCIE_ADDRESS_ALIGN_BYTES, 0);
  }
  uint32_t noc_dram_address_align_bytes() const {
    return GetField<uint32_t>(VT_NOC_DRAM_ADDRESS_ALIGN_BYTES, 0);
  }
  uint32_t l1_unreserved_base() const {
    return GetField<uint32_t>(VT_L1_UNRESERVED_BASE, 0);
  }
  uint32_t erisc_l1_unreserved_base() const {
    return GetField<uint32_t>(VT_ERISC_L1_UNRESERVED_BASE, 0);
  }
  uint32_t dram_unreserved_base() const {
    return GetField<uint32_t>(VT_DRAM_UNRESERVED_BASE, 0);
  }
  uint32_t dram_unreserved_end() const {
    return GetField<uint32_t>(VT_DRAM_UNRESERVED_END, 0);
  }
  const tt::target::ChipPhysicalCores *physical_cores() const {
    return GetPointer<const tt::target::ChipPhysicalCores *>(VT_PHYSICAL_CORES);
  }
  const ::flatbuffers::Vector<tt::target::DataType> *supported_data_types() const {
    return GetPointer<const ::flatbuffers::Vector<tt::target::DataType> *>(VT_SUPPORTED_DATA_TYPES);
  }
  const ::flatbuffers::Vector<const tt::target::Dim2d *> *supported_tile_sizes() const {
    return GetPointer<const ::flatbuffers::Vector<const tt::target::Dim2d *> *>(VT_SUPPORTED_TILE_SIZES);
  }
  uint32_t num_cbs() const {
    return GetField<uint32_t>(VT_NUM_CBS, 0);
  }
  bool Verify(::flatbuffers::Verifier &verifier) const {
    return VerifyTableStart(verifier) &&
           VerifyField<uint32_t>(verifier, VT_ARCH, 4) &&
           VerifyField<tt::target::Dim2d>(verifier, VT_GRID_SIZE, 4) &&
           VerifyField<uint64_t>(verifier, VT_L1_SIZE, 8) &&
           VerifyField<uint32_t>(verifier, VT_NUM_DRAM_CHANNELS, 4) &&
           VerifyField<uint64_t>(verifier, VT_DRAM_CHANNEL_SIZE, 8) &&
           VerifyField<uint32_t>(verifier, VT_NOC_L1_ADDRESS_ALIGN_BYTES, 4) &&
           VerifyField<uint32_t>(verifier, VT_PCIE_ADDRESS_ALIGN_BYTES, 4) &&
           VerifyField<uint32_t>(verifier, VT_NOC_DRAM_ADDRESS_ALIGN_BYTES, 4) &&
           VerifyField<uint32_t>(verifier, VT_L1_UNRESERVED_BASE, 4) &&
           VerifyField<uint32_t>(verifier, VT_ERISC_L1_UNRESERVED_BASE, 4) &&
           VerifyField<uint32_t>(verifier, VT_DRAM_UNRESERVED_BASE, 4) &&
           VerifyField<uint32_t>(verifier, VT_DRAM_UNRESERVED_END, 4) &&
           VerifyOffset(verifier, VT_PHYSICAL_CORES) &&
           verifier.VerifyTable(physical_cores()) &&
           VerifyOffset(verifier, VT_SUPPORTED_DATA_TYPES) &&
           verifier.VerifyVector(supported_data_types()) &&
           VerifyOffset(verifier, VT_SUPPORTED_TILE_SIZES) &&
           verifier.VerifyVector(supported_tile_sizes()) &&
           VerifyField<uint32_t>(verifier, VT_NUM_CBS, 4) &&
           verifier.EndTable();
  }
};
 
struct ChipDescBuilder {
  typedef ChipDesc Table;
  ::flatbuffers::FlatBufferBuilder &fbb_;
  ::flatbuffers::uoffset_t start_;
  void add_arch(tt::target::Arch arch) {
    fbb_.AddElement<uint32_t>(ChipDesc::VT_ARCH, static_cast<uint32_t>(arch), 0);
  }
  void add_grid_size(const tt::target::Dim2d *grid_size) {
    fbb_.AddStruct(ChipDesc::VT_GRID_SIZE, grid_size);
  }
  void add_l1_size(uint64_t l1_size) {
    fbb_.AddElement<uint64_t>(ChipDesc::VT_L1_SIZE, l1_size, 0);
  }
  void add_num_dram_channels(uint32_t num_dram_channels) {
    fbb_.AddElement<uint32_t>(ChipDesc::VT_NUM_DRAM_CHANNELS, num_dram_channels, 0);
  }
  void add_dram_channel_size(uint64_t dram_channel_size) {
    fbb_.AddElement<uint64_t>(ChipDesc::VT_DRAM_CHANNEL_SIZE, dram_channel_size, 0);
  }
  void add_noc_l1_address_align_bytes(uint32_t noc_l1_address_align_bytes) {
    fbb_.AddElement<uint32_t>(ChipDesc::VT_NOC_L1_ADDRESS_ALIGN_BYTES, noc_l1_address_align_bytes, 0);
  }
  void add_pcie_address_align_bytes(uint32_t pcie_address_align_bytes) {
    fbb_.AddElement<uint32_t>(ChipDesc::VT_PCIE_ADDRESS_ALIGN_BYTES, pcie_address_align_bytes, 0);
  }
  void add_noc_dram_address_align_bytes(uint32_t noc_dram_address_align_bytes) {
    fbb_.AddElement<uint32_t>(ChipDesc::VT_NOC_DRAM_ADDRESS_ALIGN_BYTES, noc_dram_address_align_bytes, 0);
  }
  void add_l1_unreserved_base(uint32_t l1_unreserved_base) {
    fbb_.AddElement<uint32_t>(ChipDesc::VT_L1_UNRESERVED_BASE, l1_unreserved_base, 0);
  }
  void add_erisc_l1_unreserved_base(uint32_t erisc_l1_unreserved_base) {
    fbb_.AddElement<uint32_t>(ChipDesc::VT_ERISC_L1_UNRESERVED_BASE, erisc_l1_unreserved_base, 0);
  }
  void add_dram_unreserved_base(uint32_t dram_unreserved_base) {
    fbb_.AddElement<uint32_t>(ChipDesc::VT_DRAM_UNRESERVED_BASE, dram_unreserved_base, 0);
  }
  void add_dram_unreserved_end(uint32_t dram_unreserved_end) {
    fbb_.AddElement<uint32_t>(ChipDesc::VT_DRAM_UNRESERVED_END, dram_unreserved_end, 0);
  }
  void add_physical_cores(::flatbuffers::Offset<tt::target::ChipPhysicalCores> physical_cores) {
    fbb_.AddOffset(ChipDesc::VT_PHYSICAL_CORES, physical_cores);
  }
  void add_supported_data_types(::flatbuffers::Offset<::flatbuffers::Vector<tt::target::DataType>> supported_data_types) {
    fbb_.AddOffset(ChipDesc::VT_SUPPORTED_DATA_TYPES, supported_data_types);
  }
  void add_supported_tile_sizes(::flatbuffers::Offset<::flatbuffers::Vector<const tt::target::Dim2d *>> supported_tile_sizes) {
    fbb_.AddOffset(ChipDesc::VT_SUPPORTED_TILE_SIZES, supported_tile_sizes);
  }
  void add_num_cbs(uint32_t num_cbs) {
    fbb_.AddElement<uint32_t>(ChipDesc::VT_NUM_CBS, num_cbs, 0);
  }
  explicit ChipDescBuilder(::flatbuffers::FlatBufferBuilder &_fbb)
        : fbb_(_fbb) {
    start_ = fbb_.StartTable();
  }
  ::flatbuffers::Offset<ChipDesc> Finish() {
    const auto end = fbb_.EndTable(start_);
    auto o = ::flatbuffers::Offset<ChipDesc>(end);
    return o;
  }
};
 
inline ::flatbuffers::Offset<ChipDesc> CreateChipDesc(
    ::flatbuffers::FlatBufferBuilder &_fbb,
    tt::target::Arch arch = tt::target::Arch::Grayskull,
    const tt::target::Dim2d *grid_size = nullptr,
    uint64_t l1_size = 0,
    uint32_t num_dram_channels = 0,
    uint64_t dram_channel_size = 0,
    uint32_t noc_l1_address_align_bytes = 0,
    uint32_t pcie_address_align_bytes = 0,
    uint32_t noc_dram_address_align_bytes = 0,
    uint32_t l1_unreserved_base = 0,
    uint32_t erisc_l1_unreserved_base = 0,
    uint32_t dram_unreserved_base = 0,
    uint32_t dram_unreserved_end = 0,
    ::flatbuffers::Offset<tt::target::ChipPhysicalCores> physical_cores = 0,
    ::flatbuffers::Offset<::flatbuffers::Vector<tt::target::DataType>> supported_data_types = 0,
    ::flatbuffers::Offset<::flatbuffers::Vector<const tt::target::Dim2d *>> supported_tile_sizes = 0,
    uint32_t num_cbs = 0) {
  ChipDescBuilder builder_(_fbb);
  builder_.add_dram_channel_size(dram_channel_size);
  builder_.add_l1_size(l1_size);
  builder_.add_num_cbs(num_cbs);
  builder_.add_supported_tile_sizes(supported_tile_sizes);
  builder_.add_supported_data_types(supported_data_types);
  builder_.add_physical_cores(physical_cores);
  builder_.add_dram_unreserved_end(dram_unreserved_end);
  builder_.add_dram_unreserved_base(dram_unreserved_base);
  builder_.add_erisc_l1_unreserved_base(erisc_l1_unreserved_base);
  builder_.add_l1_unreserved_base(l1_unreserved_base);
  builder_.add_noc_dram_address_align_bytes(noc_dram_address_align_bytes);
  builder_.add_pcie_address_align_bytes(pcie_address_align_bytes);
  builder_.add_noc_l1_address_align_bytes(noc_l1_address_align_bytes);
  builder_.add_num_dram_channels(num_dram_channels);
  builder_.add_grid_size(grid_size);
  builder_.add_arch(arch);
  return builder_.Finish();
}
 
struct ChipDesc::Traits {
  using type = ChipDesc;
  static auto constexpr Create = CreateChipDesc;
};
 
inline ::flatbuffers::Offset<ChipDesc> CreateChipDescDirect(
    ::flatbuffers::FlatBufferBuilder &_fbb,
    tt::target::Arch arch = tt::target::Arch::Grayskull,
    const tt::target::Dim2d *grid_size = nullptr,
    uint64_t l1_size = 0,
    uint32_t num_dram_channels = 0,
    uint64_t dram_channel_size = 0,
    uint32_t noc_l1_address_align_bytes = 0,
    uint32_t pcie_address_align_bytes = 0,
    uint32_t noc_dram_address_align_bytes = 0,
    uint32_t l1_unreserved_base = 0,
    uint32_t erisc_l1_unreserved_base = 0,
    uint32_t dram_unreserved_base = 0,
    uint32_t dram_unreserved_end = 0,
    ::flatbuffers::Offset<tt::target::ChipPhysicalCores> physical_cores = 0,
    const std::vector<tt::target::DataType> *supported_data_types = nullptr,
    const std::vector<tt::target::Dim2d> *supported_tile_sizes = nullptr,
    uint32_t num_cbs = 0) {
  auto supported_data_types__ = supported_data_types ? _fbb.CreateVector<tt::target::DataType>(*supported_data_types) : 0;
  auto supported_tile_sizes__ = supported_tile_sizes ? _fbb.CreateVectorOfStructs<tt::target::Dim2d>(*supported_tile_sizes) : 0;
  return tt::target::CreateChipDesc(
      _fbb,
      arch,
      grid_size,
      l1_size,
      num_dram_channels,
      dram_channel_size,
      noc_l1_address_align_bytes,
      pcie_address_align_bytes,
      noc_dram_address_align_bytes,
      l1_unreserved_base,
      erisc_l1_unreserved_base,
      dram_unreserved_base,
      dram_unreserved_end,
      physical_cores,
      supported_data_types__,
      supported_tile_sizes__,
      num_cbs);
}
 
struct ChipPhysicalCores FLATBUFFERS_FINAL_CLASS : private ::flatbuffers::Table {
  typedef ChipPhysicalCoresBuilder Builder;
  struct Traits;
  enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE {
    VT_WORKER = 4,
    VT_DRAM = 6,
    VT_ETH = 8,
    VT_ETH_INACTIVE = 10
  };
  const ::flatbuffers::Vector<const tt::target::Dim2d *> *worker() const {
    return GetPointer<const ::flatbuffers::Vector<const tt::target::Dim2d *> *>(VT_WORKER);
  }
  const ::flatbuffers::Vector<const tt::target::Dim2d *> *dram() const {
    return GetPointer<const ::flatbuffers::Vector<const tt::target::Dim2d *> *>(VT_DRAM);
  }
  const ::flatbuffers::Vector<const tt::target::Dim2d *> *eth() const {
    return GetPointer<const ::flatbuffers::Vector<const tt::target::Dim2d *> *>(VT_ETH);
  }
  const ::flatbuffers::Vector<const tt::target::Dim2d *> *eth_inactive() const {
    return GetPointer<const ::flatbuffers::Vector<const tt::target::Dim2d *> *>(VT_ETH_INACTIVE);
  }
  bool Verify(::flatbuffers::Verifier &verifier) const {
    return VerifyTableStart(verifier) &&
           VerifyOffset(verifier, VT_WORKER) &&
           verifier.VerifyVector(worker()) &&
           VerifyOffset(verifier, VT_DRAM) &&
           verifier.VerifyVector(dram()) &&
           VerifyOffset(verifier, VT_ETH) &&
           verifier.VerifyVector(eth()) &&
           VerifyOffset(verifier, VT_ETH_INACTIVE) &&
           verifier.VerifyVector(eth_inactive()) &&
           verifier.EndTable();
  }
};
 
struct ChipPhysicalCoresBuilder {
  typedef ChipPhysicalCores Table;
  ::flatbuffers::FlatBufferBuilder &fbb_;
  ::flatbuffers::uoffset_t start_;
  void add_worker(::flatbuffers::Offset<::flatbuffers::Vector<const tt::target::Dim2d *>> worker) {
    fbb_.AddOffset(ChipPhysicalCores::VT_WORKER, worker);
  }
  void add_dram(::flatbuffers::Offset<::flatbuffers::Vector<const tt::target::Dim2d *>> dram) {
    fbb_.AddOffset(ChipPhysicalCores::VT_DRAM, dram);
  }
  void add_eth(::flatbuffers::Offset<::flatbuffers::Vector<const tt::target::Dim2d *>> eth) {
    fbb_.AddOffset(ChipPhysicalCores::VT_ETH, eth);
  }
  void add_eth_inactive(::flatbuffers::Offset<::flatbuffers::Vector<const tt::target::Dim2d *>> eth_inactive) {
    fbb_.AddOffset(ChipPhysicalCores::VT_ETH_INACTIVE, eth_inactive);
  }
  explicit ChipPhysicalCoresBuilder(::flatbuffers::FlatBufferBuilder &_fbb)
        : fbb_(_fbb) {
    start_ = fbb_.StartTable();
  }
  ::flatbuffers::Offset<ChipPhysicalCores> Finish() {
    const auto end = fbb_.EndTable(start_);
    auto o = ::flatbuffers::Offset<ChipPhysicalCores>(end);
    return o;
  }
};
 
inline ::flatbuffers::Offset<ChipPhysicalCores> CreateChipPhysicalCores(
    ::flatbuffers::FlatBufferBuilder &_fbb,
    ::flatbuffers::Offset<::flatbuffers::Vector<const tt::target::Dim2d *>> worker = 0,
    ::flatbuffers::Offset<::flatbuffers::Vector<const tt::target::Dim2d *>> dram = 0,
    ::flatbuffers::Offset<::flatbuffers::Vector<const tt::target::Dim2d *>> eth = 0,
    ::flatbuffers::Offset<::flatbuffers::Vector<const tt::target::Dim2d *>> eth_inactive = 0) {
  ChipPhysicalCoresBuilder builder_(_fbb);
  builder_.add_eth_inactive(eth_inactive);
  builder_.add_eth(eth);
  builder_.add_dram(dram);
  builder_.add_worker(worker);
  return builder_.Finish();
}
 
struct ChipPhysicalCores::Traits {
  using type = ChipPhysicalCores;
  static auto constexpr Create = CreateChipPhysicalCores;
};
 
inline ::flatbuffers::Offset<ChipPhysicalCores> CreateChipPhysicalCoresDirect(
    ::flatbuffers::FlatBufferBuilder &_fbb,
    const std::vector<tt::target::Dim2d> *worker = nullptr,
    const std::vector<tt::target::Dim2d> *dram = nullptr,
    const std::vector<tt::target::Dim2d> *eth = nullptr,
    const std::vector<tt::target::Dim2d> *eth_inactive = nullptr) {
  auto worker__ = worker ? _fbb.CreateVectorOfStructs<tt::target::Dim2d>(*worker) : 0;
  auto dram__ = dram ? _fbb.CreateVectorOfStructs<tt::target::Dim2d>(*dram) : 0;
  auto eth__ = eth ? _fbb.CreateVectorOfStructs<tt::target::Dim2d>(*eth) : 0;
  auto eth_inactive__ = eth_inactive ? _fbb.CreateVectorOfStructs<tt::target::Dim2d>(*eth_inactive) : 0;
  return tt::target::CreateChipPhysicalCores(
      _fbb,
      worker__,
      dram__,
      eth__,
      eth_inactive__);
}
 
struct CPUDesc FLATBUFFERS_FINAL_CLASS : private ::flatbuffers::Table {
  typedef CPUDescBuilder Builder;
  struct Traits;
  enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE {
    VT_ROLE = 4,
    VT_TARGET_TRIPLE = 6
  };
  tt::target::CPURole role() const {
    return static_cast<tt::target::CPURole>(GetField<uint8_t>(VT_ROLE, 0));
  }
  const ::flatbuffers::String *target_triple() const {
    return GetPointer<const ::flatbuffers::String *>(VT_TARGET_TRIPLE);
  }
  bool Verify(::flatbuffers::Verifier &verifier) const {
    return VerifyTableStart(verifier) &&
           VerifyField<uint8_t>(verifier, VT_ROLE, 1) &&
           VerifyOffset(verifier, VT_TARGET_TRIPLE) &&
           verifier.VerifyString(target_triple()) &&
           verifier.EndTable();
  }
};
 
struct CPUDescBuilder {
  typedef CPUDesc Table;
  ::flatbuffers::FlatBufferBuilder &fbb_;
  ::flatbuffers::uoffset_t start_;
  void add_role(tt::target::CPURole role) {
    fbb_.AddElement<uint8_t>(CPUDesc::VT_ROLE, static_cast<uint8_t>(role), 0);
  }
  void add_target_triple(::flatbuffers::Offset<::flatbuffers::String> target_triple) {
    fbb_.AddOffset(CPUDesc::VT_TARGET_TRIPLE, target_triple);
  }
  explicit CPUDescBuilder(::flatbuffers::FlatBufferBuilder &_fbb)
        : fbb_(_fbb) {
    start_ = fbb_.StartTable();
  }
  ::flatbuffers::Offset<CPUDesc> Finish() {
    const auto end = fbb_.EndTable(start_);
    auto o = ::flatbuffers::Offset<CPUDesc>(end);
    return o;
  }
};
 
inline ::flatbuffers::Offset<CPUDesc> CreateCPUDesc(
    ::flatbuffers::FlatBufferBuilder &_fbb,
    tt::target::CPURole role = tt::target::CPURole::Host,
    ::flatbuffers::Offset<::flatbuffers::String> target_triple = 0) {
  CPUDescBuilder builder_(_fbb);
  builder_.add_target_triple(target_triple);
  builder_.add_role(role);
  return builder_.Finish();
}
 
struct CPUDesc::Traits {
  using type = CPUDesc;
  static auto constexpr Create = CreateCPUDesc;
};
 
inline ::flatbuffers::Offset<CPUDesc> CreateCPUDescDirect(
    ::flatbuffers::FlatBufferBuilder &_fbb,
    tt::target::CPURole role = tt::target::CPURole::Host,
    const char *target_triple = nullptr) {
  auto target_triple__ = target_triple ? _fbb.CreateString(target_triple) : 0;
  return tt::target::CreateCPUDesc(
      _fbb,
      role,
      target_triple__);
}
 
struct SystemDesc FLATBUFFERS_FINAL_CLASS : private ::flatbuffers::Table {
  typedef SystemDescBuilder Builder;
  struct Traits;
  enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE {
    VT_CPU_DESCS = 4,
    VT_CHIP_DESCS = 6,
    VT_CHIP_DESC_INDICES = 8,
    VT_CHIP_CAPABILITIES = 10,
    VT_CHIP_COORDS = 12,
    VT_CHIP_CHANNELS = 14
  };
  const ::flatbuffers::Vector<::flatbuffers::Offset<tt::target::CPUDesc>> *cpu_descs() const {
    return GetPointer<const ::flatbuffers::Vector<::flatbuffers::Offset<tt::target::CPUDesc>> *>(VT_CPU_DESCS);
  }
  const ::flatbuffers::Vector<::flatbuffers::Offset<tt::target::ChipDesc>> *chip_descs() const {
    return GetPointer<const ::flatbuffers::Vector<::flatbuffers::Offset<tt::target::ChipDesc>> *>(VT_CHIP_DESCS);
  }
  const ::flatbuffers::Vector<uint32_t> *chip_desc_indices() const {
    return GetPointer<const ::flatbuffers::Vector<uint32_t> *>(VT_CHIP_DESC_INDICES);
  }
  const ::flatbuffers::Vector<tt::target::ChipCapability> *chip_capabilities() const {
    return GetPointer<const ::flatbuffers::Vector<tt::target::ChipCapability> *>(VT_CHIP_CAPABILITIES);
  }
  const ::flatbuffers::Vector<const tt::target::ChipCoord *> *chip_coords() const {
    return GetPointer<const ::flatbuffers::Vector<const tt::target::ChipCoord *> *>(VT_CHIP_COORDS);
  }
  const ::flatbuffers::Vector<const tt::target::ChipChannel *> *chip_channels() const {
    return GetPointer<const ::flatbuffers::Vector<const tt::target::ChipChannel *> *>(VT_CHIP_CHANNELS);
  }
  bool Verify(::flatbuffers::Verifier &verifier) const {
    return VerifyTableStart(verifier) &&
           VerifyOffset(verifier, VT_CPU_DESCS) &&
           verifier.VerifyVector(cpu_descs()) &&
           verifier.VerifyVectorOfTables(cpu_descs()) &&
           VerifyOffset(verifier, VT_CHIP_DESCS) &&
           verifier.VerifyVector(chip_descs()) &&
           verifier.VerifyVectorOfTables(chip_descs()) &&
           VerifyOffset(verifier, VT_CHIP_DESC_INDICES) &&
           verifier.VerifyVector(chip_desc_indices()) &&
           VerifyOffset(verifier, VT_CHIP_CAPABILITIES) &&
           verifier.VerifyVector(chip_capabilities()) &&
           VerifyOffset(verifier, VT_CHIP_COORDS) &&
           verifier.VerifyVector(chip_coords()) &&
           VerifyOffset(verifier, VT_CHIP_CHANNELS) &&
           verifier.VerifyVector(chip_channels()) &&
           verifier.EndTable();
  }
};
 
struct SystemDescBuilder {
  typedef SystemDesc Table;
  ::flatbuffers::FlatBufferBuilder &fbb_;
  ::flatbuffers::uoffset_t start_;
  void add_cpu_descs(::flatbuffers::Offset<::flatbuffers::Vector<::flatbuffers::Offset<tt::target::CPUDesc>>> cpu_descs) {
    fbb_.AddOffset(SystemDesc::VT_CPU_DESCS, cpu_descs);
  }
  void add_chip_descs(::flatbuffers::Offset<::flatbuffers::Vector<::flatbuffers::Offset<tt::target::ChipDesc>>> chip_descs) {
    fbb_.AddOffset(SystemDesc::VT_CHIP_DESCS, chip_descs);
  }
  void add_chip_desc_indices(::flatbuffers::Offset<::flatbuffers::Vector<uint32_t>> chip_desc_indices) {
    fbb_.AddOffset(SystemDesc::VT_CHIP_DESC_INDICES, chip_desc_indices);
  }
  void add_chip_capabilities(::flatbuffers::Offset<::flatbuffers::Vector<tt::target::ChipCapability>> chip_capabilities) {
    fbb_.AddOffset(SystemDesc::VT_CHIP_CAPABILITIES, chip_capabilities);
  }
  void add_chip_coords(::flatbuffers::Offset<::flatbuffers::Vector<const tt::target::ChipCoord *>> chip_coords) {
    fbb_.AddOffset(SystemDesc::VT_CHIP_COORDS, chip_coords);
  }
  void add_chip_channels(::flatbuffers::Offset<::flatbuffers::Vector<const tt::target::ChipChannel *>> chip_channels) {
    fbb_.AddOffset(SystemDesc::VT_CHIP_CHANNELS, chip_channels);
  }
  explicit SystemDescBuilder(::flatbuffers::FlatBufferBuilder &_fbb)
        : fbb_(_fbb) {
    start_ = fbb_.StartTable();
  }
  ::flatbuffers::Offset<SystemDesc> Finish() {
    const auto end = fbb_.EndTable(start_);
    auto o = ::flatbuffers::Offset<SystemDesc>(end);
    return o;
  }
};
 
inline ::flatbuffers::Offset<SystemDesc> CreateSystemDesc(
    ::flatbuffers::FlatBufferBuilder &_fbb,
    ::flatbuffers::Offset<::flatbuffers::Vector<::flatbuffers::Offset<tt::target::CPUDesc>>> cpu_descs = 0,
    ::flatbuffers::Offset<::flatbuffers::Vector<::flatbuffers::Offset<tt::target::ChipDesc>>> chip_descs = 0,
    ::flatbuffers::Offset<::flatbuffers::Vector<uint32_t>> chip_desc_indices = 0,
    ::flatbuffers::Offset<::flatbuffers::Vector<tt::target::ChipCapability>> chip_capabilities = 0,
    ::flatbuffers::Offset<::flatbuffers::Vector<const tt::target::ChipCoord *>> chip_coords = 0,
    ::flatbuffers::Offset<::flatbuffers::Vector<const tt::target::ChipChannel *>> chip_channels = 0) {
  SystemDescBuilder builder_(_fbb);
  builder_.add_chip_channels(chip_channels);
  builder_.add_chip_coords(chip_coords);
  builder_.add_chip_capabilities(chip_capabilities);
  builder_.add_chip_desc_indices(chip_desc_indices);
  builder_.add_chip_descs(chip_descs);
  builder_.add_cpu_descs(cpu_descs);
  return builder_.Finish();
}
 
struct SystemDesc::Traits {
  using type = SystemDesc;
  static auto constexpr Create = CreateSystemDesc;
};
 
inline ::flatbuffers::Offset<SystemDesc> CreateSystemDescDirect(
    ::flatbuffers::FlatBufferBuilder &_fbb,
    const std::vector<::flatbuffers::Offset<tt::target::CPUDesc>> *cpu_descs = nullptr,
    const std::vector<::flatbuffers::Offset<tt::target::ChipDesc>> *chip_descs = nullptr,
    const std::vector<uint32_t> *chip_desc_indices = nullptr,
    const std::vector<tt::target::ChipCapability> *chip_capabilities = nullptr,
    const std::vector<tt::target::ChipCoord> *chip_coords = nullptr,
    const std::vector<tt::target::ChipChannel> *chip_channels = nullptr) {
  auto cpu_descs__ = cpu_descs ? _fbb.CreateVector<::flatbuffers::Offset<tt::target::CPUDesc>>(*cpu_descs) : 0;
  auto chip_descs__ = chip_descs ? _fbb.CreateVector<::flatbuffers::Offset<tt::target::ChipDesc>>(*chip_descs) : 0;
  auto chip_desc_indices__ = chip_desc_indices ? _fbb.CreateVector<uint32_t>(*chip_desc_indices) : 0;
  auto chip_capabilities__ = chip_capabilities ? _fbb.CreateVector<tt::target::ChipCapability>(*chip_capabilities) : 0;
  auto chip_coords__ = chip_coords ? _fbb.CreateVectorOfStructs<tt::target::ChipCoord>(*chip_coords) : 0;
  auto chip_channels__ = chip_channels ? _fbb.CreateVectorOfStructs<tt::target::ChipChannel>(*chip_channels) : 0;
  return tt::target::CreateSystemDesc(
      _fbb,
      cpu_descs__,
      chip_descs__,
      chip_desc_indices__,
      chip_capabilities__,
      chip_coords__,
      chip_channels__);
}
 
struct DeviceRef FLATBUFFERS_FINAL_CLASS : private ::flatbuffers::Table {
  typedef DeviceRefBuilder Builder;
  struct Traits;
  enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE {
    VT_GLOBAL_ID = 4
  };
  uint32_t global_id() const {
    return GetField<uint32_t>(VT_GLOBAL_ID, 0);
  }
  bool Verify(::flatbuffers::Verifier &verifier) const {
    return VerifyTableStart(verifier) &&
           VerifyField<uint32_t>(verifier, VT_GLOBAL_ID, 4) &&
           verifier.EndTable();
  }
};
 
struct DeviceRefBuilder {
  typedef DeviceRef Table;
  ::flatbuffers::FlatBufferBuilder &fbb_;
  ::flatbuffers::uoffset_t start_;
  void add_global_id(uint32_t global_id) {
    fbb_.AddElement<uint32_t>(DeviceRef::VT_GLOBAL_ID, global_id, 0);
  }
  explicit DeviceRefBuilder(::flatbuffers::FlatBufferBuilder &_fbb)
        : fbb_(_fbb) {
    start_ = fbb_.StartTable();
  }
  ::flatbuffers::Offset<DeviceRef> Finish() {
    const auto end = fbb_.EndTable(start_);
    auto o = ::flatbuffers::Offset<DeviceRef>(end);
    return o;
  }
};
 
inline ::flatbuffers::Offset<DeviceRef> CreateDeviceRef(
    ::flatbuffers::FlatBufferBuilder &_fbb,
    uint32_t global_id = 0) {
  DeviceRefBuilder builder_(_fbb);
  builder_.add_global_id(global_id);
  return builder_.Finish();
}
 
struct DeviceRef::Traits {
  using type = DeviceRef;
  static auto constexpr Create = CreateDeviceRef;
};
 
struct EventRef FLATBUFFERS_FINAL_CLASS : private ::flatbuffers::Table {
  typedef EventRefBuilder Builder;
  struct Traits;
  enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE {
    VT_GLOBAL_ID = 4
  };
  uint32_t global_id() const {
    return GetField<uint32_t>(VT_GLOBAL_ID, 0);
  }
  bool Verify(::flatbuffers::Verifier &verifier) const {
    return VerifyTableStart(verifier) &&
           VerifyField<uint32_t>(verifier, VT_GLOBAL_ID, 4) &&
           verifier.EndTable();
  }
};
 
struct EventRefBuilder {
  typedef EventRef Table;
  ::flatbuffers::FlatBufferBuilder &fbb_;
  ::flatbuffers::uoffset_t start_;
  void add_global_id(uint32_t global_id) {
    fbb_.AddElement<uint32_t>(EventRef::VT_GLOBAL_ID, global_id, 0);
  }
  explicit EventRefBuilder(::flatbuffers::FlatBufferBuilder &_fbb)
        : fbb_(_fbb) {
    start_ = fbb_.StartTable();
  }
  ::flatbuffers::Offset<EventRef> Finish() {
    const auto end = fbb_.EndTable(start_);
    auto o = ::flatbuffers::Offset<EventRef>(end);
    return o;
  }
};
 
inline ::flatbuffers::Offset<EventRef> CreateEventRef(
    ::flatbuffers::FlatBufferBuilder &_fbb,
    uint32_t global_id = 0) {
  EventRefBuilder builder_(_fbb);
  builder_.add_global_id(global_id);
  return builder_.Finish();
}
 
struct EventRef::Traits {
  using type = EventRef;
  static auto constexpr Create = CreateEventRef;
};
 
struct DynamicLib FLATBUFFERS_FINAL_CLASS : private ::flatbuffers::Table {
  typedef DynamicLibBuilder Builder;
  struct Traits;
  enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE {
    VT_DYLIB_ID = 4,
    VT_RAW_FILE = 6
  };
  uint32_t dylib_id() const {
    return GetField<uint32_t>(VT_DYLIB_ID, 0);
  }
  const ::flatbuffers::Vector<uint8_t> *raw_file() const {
    return GetPointer<const ::flatbuffers::Vector<uint8_t> *>(VT_RAW_FILE);
  }
  bool Verify(::flatbuffers::Verifier &verifier) const {
    return VerifyTableStart(verifier) &&
           VerifyField<uint32_t>(verifier, VT_DYLIB_ID, 4) &&
           VerifyOffset(verifier, VT_RAW_FILE) &&
           verifier.VerifyVector(raw_file()) &&
           verifier.EndTable();
  }
};
 
struct DynamicLibBuilder {
  typedef DynamicLib Table;
  ::flatbuffers::FlatBufferBuilder &fbb_;
  ::flatbuffers::uoffset_t start_;
  void add_dylib_id(uint32_t dylib_id) {
    fbb_.AddElement<uint32_t>(DynamicLib::VT_DYLIB_ID, dylib_id, 0);
  }
  void add_raw_file(::flatbuffers::Offset<::flatbuffers::Vector<uint8_t>> raw_file) {
    fbb_.AddOffset(DynamicLib::VT_RAW_FILE, raw_file);
  }
  explicit DynamicLibBuilder(::flatbuffers::FlatBufferBuilder &_fbb)
        : fbb_(_fbb) {
    start_ = fbb_.StartTable();
  }
  ::flatbuffers::Offset<DynamicLib> Finish() {
    const auto end = fbb_.EndTable(start_);
    auto o = ::flatbuffers::Offset<DynamicLib>(end);
    return o;
  }
};
 
inline ::flatbuffers::Offset<DynamicLib> CreateDynamicLib(
    ::flatbuffers::FlatBufferBuilder &_fbb,
    uint32_t dylib_id = 0,
    ::flatbuffers::Offset<::flatbuffers::Vector<uint8_t>> raw_file = 0) {
  DynamicLibBuilder builder_(_fbb);
  builder_.add_raw_file(raw_file);
  builder_.add_dylib_id(dylib_id);
  return builder_.Finish();
}
 
struct DynamicLib::Traits {
  using type = DynamicLib;
  static auto constexpr Create = CreateDynamicLib;
};
 
inline ::flatbuffers::Offset<DynamicLib> CreateDynamicLibDirect(
    ::flatbuffers::FlatBufferBuilder &_fbb,
    uint32_t dylib_id = 0,
    const std::vector<uint8_t> *raw_file = nullptr) {
  auto raw_file__ = raw_file ? _fbb.CreateVector<uint8_t>(*raw_file) : 0;
  return tt::target::CreateDynamicLib(
      _fbb,
      dylib_id,
      raw_file__);
}
 
}  // namespace target
}  // namespace tt
 
#endif  // FLATBUFFERS_GENERATED_TYPES_TT_TARGET_H_