types_generated.h File Reference

#include "flatbuffers/flatbuffers.h"

Go to the source code of this file.

Classes
struct	tt::target::Dim2d::Traits
struct	tt::target::Dim2dRange::Traits
struct	tt::target::ChipCoord::Traits
struct	tt::target::ChipChannel::Traits
struct	tt::target::FLATBUFFERS_FINAL_CLASS
struct	tt::target::ChipDescBuilder
struct	tt::target::ChipDesc::Traits
struct	tt::target::ChipPhysicalCoresBuilder
struct	tt::target::ChipPhysicalCores::Traits
struct	tt::target::CPUDescBuilder
struct	tt::target::CPUDesc::Traits
struct	tt::target::SystemDescBuilder
struct	tt::target::SystemDesc::Traits
struct	tt::target::DeviceRefBuilder
struct	tt::target::DeviceRef::Traits
struct	tt::target::EventRefBuilder
struct	tt::target::EventRef::Traits
struct	tt::target::DynamicLibBuilder
struct	tt::target::DynamicLib::Traits

Namespaces
	tt
	tt::target

Enumerations
enum class	tt::target::Arch : uint32_t {   tt::target::Grayskull = 0 , tt::target::Wormhole_b0 = 1 , tt::target::Blackhole = 2 , tt::target::MIN = Grayskull ,   tt::target::MAX = Blackhole }
enum class	tt::target::DataType : uint16_t {   tt::target::Float32 = 0 , tt::target::Float16 = 1 , tt::target::BFloat16 = 2 , tt::target::BFP_Float8 = 3 ,   tt::target::BFP_BFloat8 = 4 , tt::target::BFP_Float4 = 5 , tt::target::BFP_BFloat4 = 6 , tt::target::BFP_Float2 = 7 ,   tt::target::BFP_BFloat2 = 8 , tt::target::UInt32 = 9 , tt::target::UInt16 = 10 , tt::target::UInt8 = 11 ,   tt::target::MIN = Float32 , tt::target::MAX = UInt8 }
enum class	tt::target::OOBVal : uint16_t {   tt::target::Undef = 0 , tt::target::Zero = 1 , tt::target::One = 2 , tt::target::Inf = 3 ,   tt::target::NegInf = 4 , tt::target::MIN = Undef , tt::target::MAX = NegInf }
enum class	tt::target::MemorySpace : uint16_t {   tt::target::System = 0 , tt::target::SystemMMIO = 1 , tt::target::DeviceDRAM = 2 , tt::target::DeviceL1 = 3 ,   tt::target::MIN = System , tt::target::MAX = DeviceL1 }
enum class	tt::target::ChipCapability : uint32_t { tt::target::PCIE = 1 , tt::target::HostMMIO = 2 , tt::target::NONE = 0 , tt::target::ANY = 3 }
enum class	tt::target::TensorLayout : uint16_t {   tt::target::RowMajor = 0 , tt::target::Tile = 1 , tt::target::Invalid = 2 , tt::target::MIN = RowMajor ,   tt::target::MAX = Invalid }
enum class	tt::target::BufferType : uint16_t {   tt::target::DRAM = 0 , tt::target::L1 = 1 , tt::target::SystemMemory = 2 , tt::target::L1Small = 3 ,   tt::target::Trace = 4 , tt::target::MIN = DRAM , tt::target::MAX = Trace }
enum class	tt::target::CPURole : uint8_t { tt::target::Host = 0 , tt::target::Device = 1 , tt::target::MIN = Host , tt::target::MAX = Device }
enum class	tt::target::MathFidelity : uint8_t {   tt::target::LoFi = 0 , tt::target::HiFi2 = 2 , tt::target::HiFi3 = 3 , tt::target::HiFi4 = 4 ,   tt::target::MIN = LoFi , tt::target::MAX = HiFi4 }

Functions
const Arch(&	tt::target::EnumValuesArch ())[3]
const char *const *	tt::target::EnumNamesArch ()
const char *	tt::target::EnumNameArch (Arch e)
const DataType(&	tt::target::EnumValuesDataType ())[12]
const char *const *	tt::target::EnumNamesDataType ()
const char *	tt::target::EnumNameDataType (DataType e)
const OOBVal(&	tt::target::EnumValuesOOBVal ())[5]
const char *const *	tt::target::EnumNamesOOBVal ()
const char *	tt::target::EnumNameOOBVal (OOBVal e)
const MemorySpace(&	tt::target::EnumValuesMemorySpace ())[4]
const char *const *	tt::target::EnumNamesMemorySpace ()
const char *	tt::target::EnumNameMemorySpace (MemorySpace e)
const ChipCapability(&	tt::target::EnumValuesChipCapability ())[2]
const char *const *	tt::target::EnumNamesChipCapability ()
const char *	tt::target::EnumNameChipCapability (ChipCapability e)
const TensorLayout(&	tt::target::EnumValuesTensorLayout ())[3]
const char *const *	tt::target::EnumNamesTensorLayout ()
const char *	tt::target::EnumNameTensorLayout (TensorLayout e)
const BufferType(&	tt::target::EnumValuesBufferType ())[5]
const char *const *	tt::target::EnumNamesBufferType ()
const char *	tt::target::EnumNameBufferType (BufferType e)
const CPURole(&	tt::target::EnumValuesCPURole ())[2]
const char *const *	tt::target::EnumNamesCPURole ()
const char *	tt::target::EnumNameCPURole (CPURole e)
const MathFidelity(&	tt::target::EnumValuesMathFidelity ())[4]
const char *const *	tt::target::EnumNamesMathFidelity ()
const char *	tt::target::EnumNameMathFidelity (MathFidelity e)
	tt::target::FLATBUFFERS_MANUALLY_ALIGNED_STRUCT (4) Dim2d FLATBUFFERS_FINAL_CLASS
	tt::target::FLATBUFFERS_STRUCT_END (Dim2d, 8)
	tt::target::FLATBUFFERS_STRUCT_END (Dim2dRange, 16)
	tt::target::FLATBUFFERS_STRUCT_END (ChipCoord, 16)
	tt::target::FLATBUFFERS_STRUCT_END (ChipChannel, 24)
inline ::flatbuffers::Offset< ChipDesc >	tt::target::CreateChipDesc (::flatbuffers::FlatBufferBuilder &_fbb, tt::target::Arch arch=tt::target::Arch::Grayskull, const tt::target::Dim2d *grid_size=nullptr, uint64_t l1_size=0, uint32_t num_dram_channels=0, uint64_t dram_channel_size=0, uint32_t noc_l1_address_align_bytes=0, uint32_t pcie_address_align_bytes=0, uint32_t noc_dram_address_align_bytes=0, uint32_t l1_unreserved_base=0, uint32_t erisc_l1_unreserved_base=0, uint32_t dram_unreserved_base=0, uint32_t dram_unreserved_end=0, ::flatbuffers::Offset< tt::target::ChipPhysicalCores > physical_cores=0, ::flatbuffers::Offset<::flatbuffers::Vector< tt::target::DataType >> supported_data_types=0, ::flatbuffers::Offset<::flatbuffers::Vector< const tt::target::Dim2d * >> supported_tile_sizes=0, uint32_t num_cbs=0)
inline ::flatbuffers::Offset< ChipDesc >	tt::target::CreateChipDescDirect (::flatbuffers::FlatBufferBuilder &_fbb, tt::target::Arch arch=tt::target::Arch::Grayskull, const tt::target::Dim2d *grid_size=nullptr, uint64_t l1_size=0, uint32_t num_dram_channels=0, uint64_t dram_channel_size=0, uint32_t noc_l1_address_align_bytes=0, uint32_t pcie_address_align_bytes=0, uint32_t noc_dram_address_align_bytes=0, uint32_t l1_unreserved_base=0, uint32_t erisc_l1_unreserved_base=0, uint32_t dram_unreserved_base=0, uint32_t dram_unreserved_end=0, ::flatbuffers::Offset< tt::target::ChipPhysicalCores > physical_cores=0, const std::vector< tt::target::DataType > *supported_data_types=nullptr, const std::vector< tt::target::Dim2d > *supported_tile_sizes=nullptr, uint32_t num_cbs=0)
inline ::flatbuffers::Offset< ChipPhysicalCores >	tt::target::CreateChipPhysicalCores (::flatbuffers::FlatBufferBuilder &_fbb, ::flatbuffers::Offset<::flatbuffers::Vector< const tt::target::Dim2d * >> worker=0, ::flatbuffers::Offset<::flatbuffers::Vector< const tt::target::Dim2d * >> dram=0, ::flatbuffers::Offset<::flatbuffers::Vector< const tt::target::Dim2d * >> eth=0, ::flatbuffers::Offset<::flatbuffers::Vector< const tt::target::Dim2d * >> eth_inactive=0)
inline ::flatbuffers::Offset< ChipPhysicalCores >	tt::target::CreateChipPhysicalCoresDirect (::flatbuffers::FlatBufferBuilder &_fbb, const std::vector< tt::target::Dim2d > *worker=nullptr, const std::vector< tt::target::Dim2d > *dram=nullptr, const std::vector< tt::target::Dim2d > *eth=nullptr, const std::vector< tt::target::Dim2d > *eth_inactive=nullptr)
inline ::flatbuffers::Offset< CPUDesc >	tt::target::CreateCPUDesc (::flatbuffers::FlatBufferBuilder &_fbb, tt::target::CPURole role=tt::target::CPURole::Host, ::flatbuffers::Offset<::flatbuffers::String > target_triple=0)
inline ::flatbuffers::Offset< CPUDesc >	tt::target::CreateCPUDescDirect (::flatbuffers::FlatBufferBuilder &_fbb, tt::target::CPURole role=tt::target::CPURole::Host, const char *target_triple=nullptr)
inline ::flatbuffers::Offset< SystemDesc >	tt::target::CreateSystemDesc (::flatbuffers::FlatBufferBuilder &_fbb, ::flatbuffers::Offset<::flatbuffers::Vector<::flatbuffers::Offset< tt::target::CPUDesc >>> cpu_descs=0, ::flatbuffers::Offset<::flatbuffers::Vector<::flatbuffers::Offset< tt::target::ChipDesc >>> chip_descs=0, ::flatbuffers::Offset<::flatbuffers::Vector< uint32_t >> chip_desc_indices=0, ::flatbuffers::Offset<::flatbuffers::Vector< tt::target::ChipCapability >> chip_capabilities=0, ::flatbuffers::Offset<::flatbuffers::Vector< const tt::target::ChipCoord * >> chip_coords=0, ::flatbuffers::Offset<::flatbuffers::Vector< const tt::target::ChipChannel * >> chip_channels=0)
inline ::flatbuffers::Offset< SystemDesc >	tt::target::CreateSystemDescDirect (::flatbuffers::FlatBufferBuilder &_fbb, const std::vector<::flatbuffers::Offset< tt::target::CPUDesc >> *cpu_descs=nullptr, const std::vector<::flatbuffers::Offset< tt::target::ChipDesc >> *chip_descs=nullptr, const std::vector< uint32_t > *chip_desc_indices=nullptr, const std::vector< tt::target::ChipCapability > *chip_capabilities=nullptr, const std::vector< tt::target::ChipCoord > *chip_coords=nullptr, const std::vector< tt::target::ChipChannel > *chip_channels=nullptr)
inline ::flatbuffers::Offset< DeviceRef >	tt::target::CreateDeviceRef (::flatbuffers::FlatBufferBuilder &_fbb, uint32_t global_id=0)
inline ::flatbuffers::Offset< EventRef >	tt::target::CreateEventRef (::flatbuffers::FlatBufferBuilder &_fbb, uint32_t global_id=0)
inline ::flatbuffers::Offset< DynamicLib >	tt::target::CreateDynamicLib (::flatbuffers::FlatBufferBuilder &_fbb, uint32_t dylib_id=0, ::flatbuffers::Offset<::flatbuffers::Vector< uint8_t >> raw_file=0)
inline ::flatbuffers::Offset< DynamicLib >	tt::target::CreateDynamicLibDirect (::flatbuffers::FlatBufferBuilder &_fbb, uint32_t dylib_id=0, const std::vector< uint8_t > *raw_file=nullptr)

Variables
	VT_ARCH = 4
	VT_GRID_SIZE = 6
	VT_L1_SIZE = 8
	VT_NUM_DRAM_CHANNELS = 10
	VT_DRAM_CHANNEL_SIZE = 12
	VT_NOC_L1_ADDRESS_ALIGN_BYTES = 14
	VT_PCIE_ADDRESS_ALIGN_BYTES = 16
	VT_NOC_DRAM_ADDRESS_ALIGN_BYTES = 18
	VT_L1_UNRESERVED_BASE = 20
	VT_ERISC_L1_UNRESERVED_BASE = 22
	VT_DRAM_UNRESERVED_BASE = 24
	VT_DRAM_UNRESERVED_END = 26
	VT_PHYSICAL_CORES = 28
	VT_SUPPORTED_DATA_TYPES = 30
	VT_SUPPORTED_TILE_SIZES = 32
	VT_WORKER = 4
	VT_DRAM = 6
	VT_ETH = 8
	VT_ROLE = 4
	VT_CPU_DESCS = 4
	VT_CHIP_DESCS = 6
	VT_CHIP_DESC_INDICES = 8
	VT_CHIP_CAPABILITIES = 10
	VT_CHIP_COORDS = 12
	VT_DYLIB_ID = 4

Variable Documentation

VT_ARCH

VT_ARCH = 4

VT_CHIP_CAPABILITIES

VT_CHIP_CAPABILITIES = 10

VT_CHIP_COORDS

VT_CHIP_COORDS = 12

VT_CHIP_DESC_INDICES

VT_CHIP_DESC_INDICES = 8

VT_CHIP_DESCS

VT_CHIP_DESCS = 6

VT_CPU_DESCS

VT_CPU_DESCS = 4

VT_DRAM

VT_DRAM = 6

VT_DRAM_CHANNEL_SIZE

VT_DRAM_CHANNEL_SIZE = 12

VT_DRAM_UNRESERVED_BASE

VT_DRAM_UNRESERVED_BASE = 24

VT_DRAM_UNRESERVED_END

VT_DRAM_UNRESERVED_END = 26

VT_DYLIB_ID

VT_DYLIB_ID = 4

VT_ERISC_L1_UNRESERVED_BASE

VT_ERISC_L1_UNRESERVED_BASE = 22

VT_ETH

VT_ETH = 8

VT_GRID_SIZE

VT_GRID_SIZE = 6

VT_L1_SIZE

VT_L1_SIZE = 8

VT_L1_UNRESERVED_BASE

VT_L1_UNRESERVED_BASE = 20

VT_NOC_DRAM_ADDRESS_ALIGN_BYTES

VT_NOC_DRAM_ADDRESS_ALIGN_BYTES = 18

VT_NOC_L1_ADDRESS_ALIGN_BYTES

VT_NOC_L1_ADDRESS_ALIGN_BYTES = 14

VT_NUM_DRAM_CHANNELS

VT_NUM_DRAM_CHANNELS = 10

VT_PCIE_ADDRESS_ALIGN_BYTES

VT_PCIE_ADDRESS_ALIGN_BYTES = 16

VT_PHYSICAL_CORES

VT_PHYSICAL_CORES = 28

VT_ROLE

VT_ROLE = 4

VT_SUPPORTED_DATA_TYPES

VT_SUPPORTED_DATA_TYPES = 30

VT_SUPPORTED_TILE_SIZES

VT_SUPPORTED_TILE_SIZES = 32

VT_WORKER

VT_WORKER = 4