| ChipDescAttrStorage(ArchAttr arch, ::llvm::ArrayRef< int64_t > grid, ::llvm::ArrayRef< int64_t > coordTranslationOffsets, unsigned l1Size, unsigned numDramChannels, unsigned dramChannelSize, unsigned nocL1AddressAlignBytes, unsigned pcieAddressAlignBytes, unsigned nocDRAMAddressAlignBytes, unsigned l1UnreservedBase, unsigned eriscL1UnreservedBase, unsigned dramUnreservedBase, unsigned dramUnreservedEnd, ChipPhysicalHelperCoresAttr chipPhysicalHelperCores, ::llvm::ArrayRef< DataTypeAttr > supportedDataTypes, ::llvm::ArrayRef< TileSizeAttr > supportedTileSizes, unsigned numCBs, unsigned numComputeThreads, unsigned numDatamovementThreads) | mlir::tt::detail::ChipDescAttrStorage | inline |
