mlir::tt::detail::ChipDescAttrStorage Struct Reference

Inheritance diagram for mlir::tt::detail::ChipDescAttrStorage:

Public Types
using	KeyTy = std::tuple< ArchAttr, ::llvm::ArrayRef< int64_t >, unsigned, unsigned, unsigned, unsigned, unsigned, unsigned, unsigned, unsigned, unsigned, unsigned, ChipPhysicalCoresAttr, ::llvm::ArrayRef< DataTypeAttr >, ::llvm::ArrayRef< TileSizeAttr >, unsigned >

Public Member Functions
	ChipDescAttrStorage (ArchAttr arch, ::llvm::ArrayRef< int64_t > grid, unsigned l1Size, unsigned numDramChannels, unsigned dramChannelSize, unsigned nocL1AddressAlignBytes, unsigned pcieAddressAlignBytes, unsigned nocDRAMAddressAlignBytes, unsigned l1UnreservedBase, unsigned eriscL1UnreservedBase, unsigned dramUnreservedBase, unsigned dramUnreservedEnd, ChipPhysicalCoresAttr chipPhysicalCores, ::llvm::ArrayRef< DataTypeAttr > supportedDataTypes, ::llvm::ArrayRef< TileSizeAttr > supportedTileSizes, unsigned numCBs)
KeyTy	getAsKey () const
bool	operator== (const KeyTy &tblgenKey) const

Static Public Member Functions
::llvm::hash_code	hashKey (const KeyTy &tblgenKey)
static ChipDescAttrStorage *	construct (::mlir::AttributeStorageAllocator &allocator, KeyTy &&tblgenKey)

Public Attributes
ArchAttr	arch
::llvm::ArrayRef< int64_t >	grid
unsigned	l1Size
unsigned	numDramChannels
unsigned	dramChannelSize
unsigned	nocL1AddressAlignBytes
unsigned	pcieAddressAlignBytes
unsigned	nocDRAMAddressAlignBytes
unsigned	l1UnreservedBase
unsigned	eriscL1UnreservedBase
unsigned	dramUnreservedBase
unsigned	dramUnreservedEnd
ChipPhysicalCoresAttr	chipPhysicalCores
::llvm::ArrayRef< DataTypeAttr >	supportedDataTypes
::llvm::ArrayRef< TileSizeAttr >	supportedTileSizes
unsigned	numCBs

Member Typedef Documentation

KeyTy

using mlir::tt::detail::ChipDescAttrStorage::KeyTy = std::tuple<ArchAttr, ::llvm::ArrayRef<int64_t>, unsigned, unsigned, unsigned, unsigned, unsigned, unsigned, unsigned, unsigned, unsigned, unsigned, ChipPhysicalCoresAttr, ::llvm::ArrayRef<DataTypeAttr>, ::llvm::ArrayRef<TileSizeAttr>, unsigned>

Constructor & Destructor Documentation

ChipDescAttrStorage()

mlir::tt::detail::ChipDescAttrStorage::ChipDescAttrStorage ( ArchAttr  arch, ::llvm::ArrayRef< int64_t >  grid, unsigned  l1Size, unsigned  numDramChannels, unsigned  dramChannelSize, unsigned  nocL1AddressAlignBytes, unsigned  pcieAddressAlignBytes, unsigned  nocDRAMAddressAlignBytes, unsigned  l1UnreservedBase, unsigned  eriscL1UnreservedBase, unsigned  dramUnreservedBase, unsigned  dramUnreservedEnd, ChipPhysicalCoresAttr  chipPhysicalCores, ::llvm::ArrayRef< DataTypeAttr >  supportedDataTypes, ::llvm::ArrayRef< TileSizeAttr >  supportedTileSizes, unsigned  numCBs  )

inline

Member Function Documentation

construct()

static ChipDescAttrStorage* mlir::tt::detail::ChipDescAttrStorage::construct ( ::mlir::AttributeStorageAllocator &  allocator, KeyTy &&  tblgenKey  )

inlinestatic

getAsKey()

KeyTy mlir::tt::detail::ChipDescAttrStorage::getAsKey ( ) const

inline

hashKey()

::llvm::hash_code mlir::tt::detail::ChipDescAttrStorage::hashKey ( const KeyTy &  tblgenKey )

inlinestatic

operator==()

bool mlir::tt::detail::ChipDescAttrStorage::operator== ( const KeyTy &  tblgenKey ) const

inline

Member Data Documentation

arch

ArchAttr mlir::tt::detail::ChipDescAttrStorage::arch

chipPhysicalCores

ChipPhysicalCoresAttr mlir::tt::detail::ChipDescAttrStorage::chipPhysicalCores

dramChannelSize

unsigned mlir::tt::detail::ChipDescAttrStorage::dramChannelSize

dramUnreservedBase

unsigned mlir::tt::detail::ChipDescAttrStorage::dramUnreservedBase

dramUnreservedEnd

unsigned mlir::tt::detail::ChipDescAttrStorage::dramUnreservedEnd

eriscL1UnreservedBase

unsigned mlir::tt::detail::ChipDescAttrStorage::eriscL1UnreservedBase

grid

::llvm::ArrayRef<int64_t> mlir::tt::detail::ChipDescAttrStorage::grid

l1Size

unsigned mlir::tt::detail::ChipDescAttrStorage::l1Size

l1UnreservedBase

unsigned mlir::tt::detail::ChipDescAttrStorage::l1UnreservedBase

nocDRAMAddressAlignBytes

unsigned mlir::tt::detail::ChipDescAttrStorage::nocDRAMAddressAlignBytes

nocL1AddressAlignBytes

unsigned mlir::tt::detail::ChipDescAttrStorage::nocL1AddressAlignBytes

numCBs

unsigned mlir::tt::detail::ChipDescAttrStorage::numCBs

numDramChannels

unsigned mlir::tt::detail::ChipDescAttrStorage::numDramChannels

pcieAddressAlignBytes

unsigned mlir::tt::detail::ChipDescAttrStorage::pcieAddressAlignBytes

supportedDataTypes

::llvm::ArrayRef<DataTypeAttr> mlir::tt::detail::ChipDescAttrStorage::supportedDataTypes

supportedTileSizes

::llvm::ArrayRef<TileSizeAttr> mlir::tt::detail::ChipDescAttrStorage::supportedTileSizes

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The documentation for this struct was generated from the following file:

• /__w/tt-mlir/tt-mlir/build/include/ttmlir/Dialect/TT/IR/TTOpsAttrDefs.cpp.inc