types_generated.h File Reference

#include "flatbuffers/flatbuffers.h"

Go to the source code of this file.

Classes
struct	tt::target::DistributedTensorConfigTraits< T >
struct	tt::target::DistributedTensorConfigTraits< tt::target::ReplicateTensor >
struct	tt::target::DistributedTensorConfigTraits< tt::target::ShardTensor >
struct	tt::target::DistributedTensorConfigTraits< tt::target::ShardTensor2D >
struct	tt::target::DistributedTensorConfigTraits< tt::target::AllGatherTensor >
struct	tt::target::Dim2d::Traits
struct	tt::target::Dim2dRange::Traits
struct	tt::target::ChipCoord::Traits
struct	tt::target::ChipChannel::Traits
struct	tt::target::FLATBUFFERS_FINAL_CLASS
struct	tt::target::ShardSpecBuilder
struct	tt::target::ShardSpec::Traits
struct	tt::target::MemoryConfigDescBuilder
struct	tt::target::MemoryConfigDesc::Traits
struct	tt::target::ReplicateTensorBuilder
struct	tt::target::ReplicateTensor::Traits
struct	tt::target::ShardTensorBuilder
struct	tt::target::ShardTensor::Traits
struct	tt::target::ShardTensor2DBuilder
struct	tt::target::ShardTensor2D::Traits
struct	tt::target::AllGatherTensorBuilder
struct	tt::target::AllGatherTensor::Traits
struct	tt::target::DistributionStrategyBuilder
struct	tt::target::DistributionStrategy::Traits
struct	tt::target::MemoryDescBuilder
struct	tt::target::MemoryDesc::Traits
struct	tt::target::LayoutDescBuilder
struct	tt::target::LayoutDesc::Traits
struct	tt::target::TensorDescBuilder
struct	tt::target::TensorDesc::Traits
struct	tt::target::CBDescBuilder
struct	tt::target::CBDesc::Traits
struct	tt::target::TensorRefBuilder
struct	tt::target::TensorRef::Traits
struct	tt::target::CBRefBuilder
struct	tt::target::CBRef::Traits
struct	tt::target::ChipDescBuilder
struct	tt::target::ChipDesc::Traits
struct	tt::target::ChipPhysicalCoresBuilder
struct	tt::target::ChipPhysicalCores::Traits
struct	tt::target::CPUDescBuilder
struct	tt::target::CPUDesc::Traits
struct	tt::target::SystemDescBuilder
struct	tt::target::SystemDesc::Traits
struct	tt::target::DeviceRefBuilder
struct	tt::target::DeviceRef::Traits
struct	tt::target::EventRefBuilder
struct	tt::target::EventRef::Traits

Namespaces
	tt
	tt::target

Enumerations
enum class	tt::target::Arch : uint32_t {   tt::target::Grayskull = 0 , tt::target::Wormhole_b0 = 1 , tt::target::Blackhole = 2 , tt::target::MIN = Grayskull ,   tt::target::MAX = Blackhole }
enum class	tt::target::DataType : uint16_t {   tt::target::Float32 = 0 , tt::target::Float16 = 1 , tt::target::BFloat16 = 2 , tt::target::BFP_Float8 = 3 ,   tt::target::BFP_BFloat8 = 4 , tt::target::BFP_Float4 = 5 , tt::target::BFP_BFloat4 = 6 , tt::target::BFP_Float2 = 7 ,   tt::target::BFP_BFloat2 = 8 , tt::target::UInt32 = 9 , tt::target::UInt16 = 10 , tt::target::UInt8 = 11 ,   tt::target::MIN = Float32 , tt::target::MAX = UInt8 }
enum class	tt::target::OOBVal : uint16_t {   tt::target::Undef = 0 , tt::target::Zero = 1 , tt::target::One = 2 , tt::target::Inf = 3 ,   tt::target::NegInf = 4 , tt::target::MIN = Undef , tt::target::MAX = NegInf }
enum class	tt::target::MemorySpace : uint16_t {   tt::target::System = 0 , tt::target::SystemMMIO = 1 , tt::target::DeviceDRAM = 2 , tt::target::DeviceL1 = 3 ,   tt::target::MIN = System , tt::target::MAX = DeviceL1 }
enum class	tt::target::ChipCapability : uint32_t { tt::target::PCIE = 1 , tt::target::HostMMIO = 2 , tt::target::NONE = 0 , tt::target::ANY = 3 }
enum class	tt::target::TensorMemoryLayout : uint16_t {   tt::target::None = 0 , tt::target::Interleaved = 1 , tt::target::SingleBank = 2 , tt::target::HeightSharded = 3 ,   tt::target::WidthSharded = 4 , tt::target::BlockSharded = 5 , tt::target::MIN = None , tt::target::MAX = BlockSharded }
enum class	tt::target::TensorLayout : uint16_t {   tt::target::RowMajor = 0 , tt::target::Tile = 1 , tt::target::Invalid = 2 , tt::target::MIN = RowMajor ,   tt::target::MAX = Invalid }
enum class	tt::target::BufferType : uint16_t {   tt::target::DRAM = 0 , tt::target::L1 = 1 , tt::target::SystemMemory = 2 , tt::target::L1Small = 3 ,   tt::target::Trace = 4 , tt::target::MIN = DRAM , tt::target::MAX = Trace }
enum class	tt::target::DistributedTensorConfig : uint8_t {   tt::target::NONE = 0 , tt::target::ReplicateTensor = 1 , tt::target::ShardTensor = 2 , tt::target::ShardTensor2D = 3 ,   tt::target::AllGatherTensor = 4 , tt::target::MIN = NONE , tt::target::MAX = AllGatherTensor }
enum class	tt::target::CPURole : uint8_t { tt::target::Host = 0 , tt::target::Device = 1 , tt::target::MIN = Host , tt::target::MAX = Device }
enum class	tt::target::MathFidelity : uint8_t {   tt::target::LoFi = 0 , tt::target::HiFi2 = 2 , tt::target::HiFi3 = 3 , tt::target::HiFi4 = 4 ,   tt::target::MIN = LoFi , tt::target::MAX = HiFi4 }

Functions
const Arch(&	tt::target::EnumValuesArch ())[3]
const char *const *	tt::target::EnumNamesArch ()
const char *	tt::target::EnumNameArch (Arch e)
const DataType(&	tt::target::EnumValuesDataType ())[12]
const char *const *	tt::target::EnumNamesDataType ()
const char *	tt::target::EnumNameDataType (DataType e)
const OOBVal(&	tt::target::EnumValuesOOBVal ())[5]
const char *const *	tt::target::EnumNamesOOBVal ()
const char *	tt::target::EnumNameOOBVal (OOBVal e)
const MemorySpace(&	tt::target::EnumValuesMemorySpace ())[4]
const char *const *	tt::target::EnumNamesMemorySpace ()
const char *	tt::target::EnumNameMemorySpace (MemorySpace e)
const ChipCapability(&	tt::target::EnumValuesChipCapability ())[2]
const char *const *	tt::target::EnumNamesChipCapability ()
const char *	tt::target::EnumNameChipCapability (ChipCapability e)
const TensorMemoryLayout(&	tt::target::EnumValuesTensorMemoryLayout ())[6]
const char *const *	tt::target::EnumNamesTensorMemoryLayout ()
const char *	tt::target::EnumNameTensorMemoryLayout (TensorMemoryLayout e)
const TensorLayout(&	tt::target::EnumValuesTensorLayout ())[3]
const char *const *	tt::target::EnumNamesTensorLayout ()
const char *	tt::target::EnumNameTensorLayout (TensorLayout e)
const BufferType(&	tt::target::EnumValuesBufferType ())[5]
const char *const *	tt::target::EnumNamesBufferType ()
const char *	tt::target::EnumNameBufferType (BufferType e)
const DistributedTensorConfig(&	tt::target::EnumValuesDistributedTensorConfig ())[5]
const char *const *	tt::target::EnumNamesDistributedTensorConfig ()
const char *	tt::target::EnumNameDistributedTensorConfig (DistributedTensorConfig e)
bool	tt::target::VerifyDistributedTensorConfig (::flatbuffers::Verifier &verifier, const void *obj, DistributedTensorConfig type)
bool	tt::target::VerifyDistributedTensorConfigVector (::flatbuffers::Verifier &verifier, const ::flatbuffers::Vector<::flatbuffers::Offset< void >> *values, const ::flatbuffers::Vector< DistributedTensorConfig > *types)
const CPURole(&	tt::target::EnumValuesCPURole ())[2]
const char *const *	tt::target::EnumNamesCPURole ()
const char *	tt::target::EnumNameCPURole (CPURole e)
const MathFidelity(&	tt::target::EnumValuesMathFidelity ())[4]
const char *const *	tt::target::EnumNamesMathFidelity ()
const char *	tt::target::EnumNameMathFidelity (MathFidelity e)
	tt::target::FLATBUFFERS_MANUALLY_ALIGNED_STRUCT (4) Dim2d FLATBUFFERS_FINAL_CLASS
	tt::target::FLATBUFFERS_STRUCT_END (Dim2d, 8)
	tt::target::FLATBUFFERS_STRUCT_END (Dim2dRange, 16)
	tt::target::FLATBUFFERS_STRUCT_END (ChipCoord, 16)
	tt::target::FLATBUFFERS_STRUCT_END (ChipChannel, 24)
inline ::flatbuffers::Offset< ShardSpec >	tt::target::CreateShardSpec (::flatbuffers::FlatBufferBuilder &_fbb, ::flatbuffers::Offset<::flatbuffers::Vector< int64_t >> shard_shape=0)
inline ::flatbuffers::Offset< ShardSpec >	tt::target::CreateShardSpecDirect (::flatbuffers::FlatBufferBuilder &_fbb, const std::vector< int64_t > *shard_shape=nullptr)
inline ::flatbuffers::Offset< MemoryConfigDesc >	tt::target::CreateMemoryConfigDesc (::flatbuffers::FlatBufferBuilder &_fbb, tt::target::TensorMemoryLayout tensor_memory_layout=tt::target::TensorMemoryLayout::None, tt::target::BufferType buffer_type=tt::target::BufferType::DRAM, ::flatbuffers::Offset< tt::target::ShardSpec > shard_spec=0)
inline ::flatbuffers::Offset< ReplicateTensor >	tt::target::CreateReplicateTensor (::flatbuffers::FlatBufferBuilder &_fbb, uint32_t replication_factor=0)
inline ::flatbuffers::Offset< ShardTensor >	tt::target::CreateShardTensor (::flatbuffers::FlatBufferBuilder &_fbb, uint32_t shard_dim=0)
inline ::flatbuffers::Offset< ShardTensor2D >	tt::target::CreateShardTensor2D (::flatbuffers::FlatBufferBuilder &_fbb, const tt::target::Dim2d *shard_mesh=nullptr)
inline ::flatbuffers::Offset< AllGatherTensor >	tt::target::CreateAllGatherTensor (::flatbuffers::FlatBufferBuilder &_fbb)
template<>
const tt::target::ReplicateTensor *	tt::target::DistributionStrategy::strategy_as< tt::target::ReplicateTensor > () const
template<>
const tt::target::ShardTensor *	tt::target::DistributionStrategy::strategy_as< tt::target::ShardTensor > () const
template<>
const tt::target::ShardTensor2D *	tt::target::DistributionStrategy::strategy_as< tt::target::ShardTensor2D > () const
template<>
const tt::target::AllGatherTensor *	tt::target::DistributionStrategy::strategy_as< tt::target::AllGatherTensor > () const
inline ::flatbuffers::Offset< DistributionStrategy >	tt::target::CreateDistributionStrategy (::flatbuffers::FlatBufferBuilder &_fbb, tt::target::DistributedTensorConfig strategy_type=tt::target::DistributedTensorConfig::NONE, ::flatbuffers::Offset< void > strategy=0)
inline ::flatbuffers::Offset< MemoryDesc >	tt::target::CreateMemoryDesc (::flatbuffers::FlatBufferBuilder &_fbb, ::flatbuffers::Offset<::flatbuffers::Vector< int32_t >> shape=0, const tt::target::Dim2d *tile_shape=nullptr, tt::target::DataType data_type=tt::target::DataType::Float32, tt::target::MemorySpace memory_space=tt::target::MemorySpace::System, tt::target::TensorMemoryLayout memory_layout=tt::target::TensorMemoryLayout::None, uint64_t size=0)
inline ::flatbuffers::Offset< MemoryDesc >	tt::target::CreateMemoryDescDirect (::flatbuffers::FlatBufferBuilder &_fbb, const std::vector< int32_t > *shape=nullptr, const tt::target::Dim2d *tile_shape=nullptr, tt::target::DataType data_type=tt::target::DataType::Float32, tt::target::MemorySpace memory_space=tt::target::MemorySpace::System, tt::target::TensorMemoryLayout memory_layout=tt::target::TensorMemoryLayout::None, uint64_t size=0)
inline ::flatbuffers::Offset< LayoutDesc >	tt::target::CreateLayoutDesc (::flatbuffers::FlatBufferBuilder &_fbb, ::flatbuffers::Offset<::flatbuffers::Vector< int32_t >> stride=0, tt::target::OOBVal oob_val=tt::target::OOBVal::Undef, ::flatbuffers::Offset<::flatbuffers::Vector< const tt::target::Dim2dRange * >> core_range_set=0, ::flatbuffers::Offset< tt::target::MemoryDesc > memory_desc=0, ::flatbuffers::Offset< tt::target::DistributionStrategy > strategy=0)
inline ::flatbuffers::Offset< LayoutDesc >	tt::target::CreateLayoutDescDirect (::flatbuffers::FlatBufferBuilder &_fbb, const std::vector< int32_t > *stride=nullptr, tt::target::OOBVal oob_val=tt::target::OOBVal::Undef, const std::vector< tt::target::Dim2dRange > *core_range_set=nullptr, ::flatbuffers::Offset< tt::target::MemoryDesc > memory_desc=0, ::flatbuffers::Offset< tt::target::DistributionStrategy > strategy=0)
inline ::flatbuffers::Offset< TensorDesc >	tt::target::CreateTensorDesc (::flatbuffers::FlatBufferBuilder &_fbb, ::flatbuffers::Offset<::flatbuffers::Vector< int32_t >> shape=0, ::flatbuffers::Offset< tt::target::LayoutDesc > layout=0)
inline ::flatbuffers::Offset< TensorDesc >	tt::target::CreateTensorDescDirect (::flatbuffers::FlatBufferBuilder &_fbb, const std::vector< int32_t > *shape=nullptr, ::flatbuffers::Offset< tt::target::LayoutDesc > layout=0)
inline ::flatbuffers::Offset< CBDesc >	tt::target::CreateCBDesc (::flatbuffers::FlatBufferBuilder &_fbb, uint32_t port=0, ::flatbuffers::Offset< tt::target::MemoryDesc > memory_desc=0, uint64_t page_size=0, uint64_t num_buffers=0)
inline ::flatbuffers::Offset< TensorRef >	tt::target::CreateTensorRef (::flatbuffers::FlatBufferBuilder &_fbb, uint32_t global_id=0, uint64_t address=0, uint64_t size=0, ::flatbuffers::Offset< tt::target::TensorDesc > desc=0)
inline ::flatbuffers::Offset< CBRef >	tt::target::CreateCBRef (::flatbuffers::FlatBufferBuilder &_fbb, uint32_t global_id=0, ::flatbuffers::Offset< tt::target::TensorRef > tensor_ref=0, uint64_t address=0, ::flatbuffers::Offset< tt::target::CBDesc > desc=0)
inline ::flatbuffers::Offset< ChipDesc >	tt::target::CreateChipDesc (::flatbuffers::FlatBufferBuilder &_fbb, tt::target::Arch arch=tt::target::Arch::Grayskull, const tt::target::Dim2d *grid_size=nullptr, uint64_t l1_size=0, uint32_t num_dram_channels=0, uint64_t dram_channel_size=0, uint32_t noc_l1_address_align_bytes=0, uint32_t pcie_address_align_bytes=0, uint32_t noc_dram_address_align_bytes=0, uint32_t l1_unreserved_base=0, uint32_t erisc_l1_unreserved_base=0, uint32_t dram_unreserved_base=0, uint32_t dram_unreserved_end=0, ::flatbuffers::Offset< tt::target::ChipPhysicalCores > physical_cores=0, ::flatbuffers::Offset<::flatbuffers::Vector< tt::target::DataType >> supported_data_types=0, ::flatbuffers::Offset<::flatbuffers::Vector< const tt::target::Dim2d * >> supported_tile_sizes=0, uint32_t num_cbs=0)
inline ::flatbuffers::Offset< ChipDesc >	tt::target::CreateChipDescDirect (::flatbuffers::FlatBufferBuilder &_fbb, tt::target::Arch arch=tt::target::Arch::Grayskull, const tt::target::Dim2d *grid_size=nullptr, uint64_t l1_size=0, uint32_t num_dram_channels=0, uint64_t dram_channel_size=0, uint32_t noc_l1_address_align_bytes=0, uint32_t pcie_address_align_bytes=0, uint32_t noc_dram_address_align_bytes=0, uint32_t l1_unreserved_base=0, uint32_t erisc_l1_unreserved_base=0, uint32_t dram_unreserved_base=0, uint32_t dram_unreserved_end=0, ::flatbuffers::Offset< tt::target::ChipPhysicalCores > physical_cores=0, const std::vector< tt::target::DataType > *supported_data_types=nullptr, const std::vector< tt::target::Dim2d > *supported_tile_sizes=nullptr, uint32_t num_cbs=0)
inline ::flatbuffers::Offset< ChipPhysicalCores >	tt::target::CreateChipPhysicalCores (::flatbuffers::FlatBufferBuilder &_fbb, ::flatbuffers::Offset<::flatbuffers::Vector< const tt::target::Dim2d * >> worker=0, ::flatbuffers::Offset<::flatbuffers::Vector< const tt::target::Dim2d * >> dram=0, ::flatbuffers::Offset<::flatbuffers::Vector< const tt::target::Dim2d * >> eth=0, ::flatbuffers::Offset<::flatbuffers::Vector< const tt::target::Dim2d * >> eth_inactive=0)
inline ::flatbuffers::Offset< ChipPhysicalCores >	tt::target::CreateChipPhysicalCoresDirect (::flatbuffers::FlatBufferBuilder &_fbb, const std::vector< tt::target::Dim2d > *worker=nullptr, const std::vector< tt::target::Dim2d > *dram=nullptr, const std::vector< tt::target::Dim2d > *eth=nullptr, const std::vector< tt::target::Dim2d > *eth_inactive=nullptr)
inline ::flatbuffers::Offset< CPUDesc >	tt::target::CreateCPUDesc (::flatbuffers::FlatBufferBuilder &_fbb, tt::target::CPURole role=tt::target::CPURole::Host, ::flatbuffers::Offset<::flatbuffers::String > target_triple=0)
inline ::flatbuffers::Offset< CPUDesc >	tt::target::CreateCPUDescDirect (::flatbuffers::FlatBufferBuilder &_fbb, tt::target::CPURole role=tt::target::CPURole::Host, const char *target_triple=nullptr)
inline ::flatbuffers::Offset< SystemDesc >	tt::target::CreateSystemDesc (::flatbuffers::FlatBufferBuilder &_fbb, ::flatbuffers::Offset<::flatbuffers::Vector<::flatbuffers::Offset< tt::target::CPUDesc >>> cpu_descs=0, ::flatbuffers::Offset<::flatbuffers::Vector<::flatbuffers::Offset< tt::target::ChipDesc >>> chip_descs=0, ::flatbuffers::Offset<::flatbuffers::Vector< uint32_t >> chip_desc_indices=0, ::flatbuffers::Offset<::flatbuffers::Vector< tt::target::ChipCapability >> chip_capabilities=0, ::flatbuffers::Offset<::flatbuffers::Vector< const tt::target::ChipCoord * >> chip_coords=0, ::flatbuffers::Offset<::flatbuffers::Vector< const tt::target::ChipChannel * >> chip_channels=0)
inline ::flatbuffers::Offset< SystemDesc >	tt::target::CreateSystemDescDirect (::flatbuffers::FlatBufferBuilder &_fbb, const std::vector<::flatbuffers::Offset< tt::target::CPUDesc >> *cpu_descs=nullptr, const std::vector<::flatbuffers::Offset< tt::target::ChipDesc >> *chip_descs=nullptr, const std::vector< uint32_t > *chip_desc_indices=nullptr, const std::vector< tt::target::ChipCapability > *chip_capabilities=nullptr, const std::vector< tt::target::ChipCoord > *chip_coords=nullptr, const std::vector< tt::target::ChipChannel > *chip_channels=nullptr)
inline ::flatbuffers::Offset< DeviceRef >	tt::target::CreateDeviceRef (::flatbuffers::FlatBufferBuilder &_fbb, uint32_t global_id=0)
inline ::flatbuffers::Offset< EventRef >	tt::target::CreateEventRef (::flatbuffers::FlatBufferBuilder &_fbb, uint32_t global_id=0)

Variables
	VT_TENSOR_MEMORY_LAYOUT = 4
	VT_BUFFER_TYPE = 6
	VT_STRATEGY_TYPE = 4
	VT_SHAPE = 4
	VT_TILE_SHAPE = 6
	VT_DATA_TYPE = 8
	VT_MEMORY_SPACE = 10
	VT_MEMORY_LAYOUT = 12
	VT_STRIDE = 4
	VT_OOB_VAL = 6
	VT_CORE_RANGE_SET = 8
	VT_MEMORY_DESC = 10
	VT_PORT = 4
	VT_PAGE_SIZE = 8
	VT_GLOBAL_ID = 4
	VT_ADDRESS = 6
	VT_SIZE = 8
	VT_TENSOR_REF = 6
	VT_ARCH = 4
	VT_GRID_SIZE = 6
	VT_L1_SIZE = 8
	VT_NUM_DRAM_CHANNELS = 10
	VT_DRAM_CHANNEL_SIZE = 12
	VT_NOC_L1_ADDRESS_ALIGN_BYTES = 14
	VT_PCIE_ADDRESS_ALIGN_BYTES = 16
	VT_NOC_DRAM_ADDRESS_ALIGN_BYTES = 18
	VT_L1_UNRESERVED_BASE = 20
	VT_ERISC_L1_UNRESERVED_BASE = 22
	VT_DRAM_UNRESERVED_BASE = 24
	VT_DRAM_UNRESERVED_END = 26
	VT_PHYSICAL_CORES = 28
	VT_SUPPORTED_DATA_TYPES = 30
	VT_SUPPORTED_TILE_SIZES = 32
	VT_WORKER = 4
	VT_DRAM = 6
	VT_ETH = 8
	VT_ROLE = 4
	VT_CPU_DESCS = 4
	VT_CHIP_DESCS = 6
	VT_CHIP_DESC_INDICES = 8
	VT_CHIP_CAPABILITIES = 10
	VT_CHIP_COORDS = 12

Variable Documentation

VT_ADDRESS

VT_ADDRESS = 6

VT_ARCH

VT_ARCH = 4

VT_BUFFER_TYPE

VT_BUFFER_TYPE = 6

VT_CHIP_CAPABILITIES

VT_CHIP_CAPABILITIES = 10

VT_CHIP_COORDS

VT_CHIP_COORDS = 12

VT_CHIP_DESC_INDICES

VT_CHIP_DESC_INDICES = 8

VT_CHIP_DESCS

VT_CHIP_DESCS = 6

VT_CORE_RANGE_SET

VT_CORE_RANGE_SET = 8

VT_CPU_DESCS

VT_CPU_DESCS = 4

VT_DATA_TYPE

VT_DATA_TYPE = 8

VT_DRAM

VT_DRAM = 6

VT_DRAM_CHANNEL_SIZE

VT_DRAM_CHANNEL_SIZE = 12

VT_DRAM_UNRESERVED_BASE

VT_DRAM_UNRESERVED_BASE = 24

VT_DRAM_UNRESERVED_END

VT_DRAM_UNRESERVED_END = 26

VT_ERISC_L1_UNRESERVED_BASE

VT_ERISC_L1_UNRESERVED_BASE = 22

VT_ETH

VT_ETH = 8

VT_GLOBAL_ID

VT_GLOBAL_ID = 4

VT_GRID_SIZE

VT_GRID_SIZE = 6

VT_L1_SIZE

VT_L1_SIZE = 8

VT_L1_UNRESERVED_BASE

VT_L1_UNRESERVED_BASE = 20

VT_MEMORY_DESC

VT_MEMORY_DESC = 10

VT_MEMORY_LAYOUT

VT_MEMORY_LAYOUT = 12

VT_MEMORY_SPACE

VT_MEMORY_SPACE = 10

VT_NOC_DRAM_ADDRESS_ALIGN_BYTES

VT_NOC_DRAM_ADDRESS_ALIGN_BYTES = 18

VT_NOC_L1_ADDRESS_ALIGN_BYTES

VT_NOC_L1_ADDRESS_ALIGN_BYTES = 14

VT_NUM_DRAM_CHANNELS

VT_NUM_DRAM_CHANNELS = 10

VT_OOB_VAL

VT_OOB_VAL = 6

VT_PAGE_SIZE

VT_PAGE_SIZE = 8

VT_PCIE_ADDRESS_ALIGN_BYTES

VT_PCIE_ADDRESS_ALIGN_BYTES = 16

VT_PHYSICAL_CORES

VT_PHYSICAL_CORES = 28

VT_PORT

VT_PORT = 4

VT_ROLE

VT_ROLE = 4

VT_SHAPE

VT_SHAPE = 4

VT_SIZE

VT_SIZE = 8

VT_STRATEGY_TYPE

VT_STRATEGY_TYPE = 4

VT_STRIDE

VT_STRIDE = 4

VT_SUPPORTED_DATA_TYPES

VT_SUPPORTED_DATA_TYPES = 30

VT_SUPPORTED_TILE_SIZES

VT_SUPPORTED_TILE_SIZES = 32

VT_TENSOR_MEMORY_LAYOUT

VT_TENSOR_MEMORY_LAYOUT = 4

VT_TENSOR_REF

VT_TENSOR_REF = 6

VT_TILE_SHAPE

VT_TILE_SHAPE = 6

VT_WORKER

VT_WORKER = 4