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TT-System-Firmware APIs 19.10.99
Tenstorrent Firmware
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#include <zephyr/kernel.h>#include <zephyr/device.h>#include <zephyr/drivers/clock_control.h>#include <zephyr/drivers/clock_control/clock_control_tt_bh.h>#include <zephyr/sys/sys_io.h>#include <zephyr/sys_clock.h>#include <zephyr/sys/util.h>#include <stdint.h>#include <zephyr/logging/log.h>
Data Structures | |
| struct | tt_bh_pll_cntl_wrapper_lock_fields |
| union | tt_bh_pll_cntl_wrapper_lock_reg |
| struct | tt_bh_pll_cntl_0_fields |
| union | tt_bh_pll_cntl_0_reg |
| struct | tt_bh_pll_cntl_1_fields |
| union | tt_bh_pll_cntl_1_reg |
| struct | tt_bh_pll_cntl_2_fields |
| union | tt_bh_pll_cntl_2_reg |
| struct | tt_bh_pll_cntl_3_fields |
| union | tt_bh_pll_cntl_3_reg |
| struct | tt_bh_pll_cntl_5_fields |
| union | tt_bh_pll_cntl_5_reg |
| struct | tt_bh_pll_use_postdiv_fields |
| union | tt_bh_pll_use_postdiv_reg |
| struct | tt_bh_pll_settings |
| struct | clock_control_tt_bh_config |
| struct | clock_control_tt_bh_data |
Variables | |
| static const struct clock_control_driver_api | clock_control_tt_bh_api |
| #define CLK_COUNTER_0_OFFSET 0x34 |
| #define CLK_COUNTER_1_OFFSET 0x38 |
| #define CLK_COUNTER_2_OFFSET 0x3C |
| #define CLK_COUNTER_3_OFFSET 0x40 |
| #define CLK_COUNTER_4_OFFSET 0x44 |
| #define CLK_COUNTER_5_OFFSET 0x48 |
| #define CLK_COUNTER_6_OFFSET 0x4C |
| #define CLK_COUNTER_7_OFFSET 0x50 |
| #define CLK_COUNTER_EN_OFFSET 0x30 |
| #define CLK_COUNTER_REFCLK_PERIOD 1000 |
| #define CLOCK_CONTROL_TT_BH_INIT | ( | _inst | ) |
| #define DT_DRV_COMPAT tenstorrent_bh_clock_control |
| #define FINE_DUTYC_ADJUST_OFFSET 0x2C |
| #define PLL_CNTL_0_OFFSET 0x00 |
| #define PLL_CNTL_1_OFFSET 0x04 |
| #define PLL_CNTL_2_OFFSET 0x08 |
| #define PLL_CNTL_3_OFFSET 0x0C |
| #define PLL_CNTL_4_OFFSET 0x10 |
| #define PLL_CNTL_5_OFFSET 0x14 |
| #define PLL_CNTL_6_OFFSET 0x18 |
| #define PLL_CNTL_WRAPPER_PLL_LOCK_REG_ADDR 0x80020040 |
| #define PLL_CNTL_WRAPPER_REFCLK_PERIOD_REG_ADDR 0x8002002C |
| #define PLL_LOCK_TIMEOUT_MS 400 |
| #define PLL_REFCLK_SEL_OFFSET 0x20 |
| #define PLL_USE_FINE_DIVIDER_1_OFFSET 0x24 |
| #define PLL_USE_FINE_DIVIDER_2_OFFSET 0x28 |
| #define PLL_USE_POSTDIV_OFFSET 0x1C |
| #define VCO_MAX_FREQ 5000 |
| #define VCO_MIN_FREQ 1600 |
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| LOG_MODULE_REGISTER | ( | clock_control_tt_bh | ) |
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