dma_arc_hs.c File Reference

#include <errno.h>
#include <string.h>
#include <stdint.h>
#include <zephyr/device.h>
#include <zephyr/drivers/dma.h>
#include <zephyr/drivers/dma/dma_arc_hs.h>
#include <zephyr/logging/log.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/barrier.h>
#include <zephyr/sys/util.h>
#include <zephyr/irq.h>
#include <zephyr/sys/atomic.h>
#include <zephyr/arch/arc/v2/aux_regs.h>
#include <zephyr/arch/common/ffs.h>
#include <zephyr/sys/__assert.h>

Include dependency graph for dma_arc_hs.c:

Data Structures
struct	arc_dma_channel
struct	arc_dma_config
struct	arc_dma_data

Macros
#define	DT_DRV_COMPAT   snps_designware_dma_arc_hs
#define	dma_addr_t   uint32_t
#define	DMA_AUX_BASE   (0xd00)
#define	DMA_C_CTRL_AUX   (0xd00 + 0x0)
#define	DMA_C_CHAN_AUX   (0xd00 + 0x1)
#define	DMA_C_SRC_AUX   (0xd00 + 0x2)
#define	DMA_C_SRC_HI_AUX   (0xd00 + 0x3)
#define	DMA_C_DST_AUX   (0xd00 + 0x4)
#define	DMA_C_DST_HI_AUX   (0xd00 + 0x5)
#define	DMA_C_ATTR_AUX   (0xd00 + 0x6)
#define	DMA_C_LEN_AUX   (0xd00 + 0x7)
#define	DMA_C_HANDLE_AUX   (0xd00 + 0x8)
#define	DMA_C_STAT_AUX   (0xd00 + 0xc)
#define	DMA_C_INTSTAT_AUX   (0xd00 + 0xd)
#define	DMA_C_INTSTAT_CLR_AUX   (0xd00 + 0xe)
#define	DMA_C_INTSTAT_DONE   (1 << 0) /* D: Transfer complete */
#define	DMA_C_INTSTAT_BUS_ERR   (1 << 1) /* B: Bus error */
#define	DMA_C_INTSTAT_OVERFLOW   (1 << 2) /* O: Channel overflow */
#define	DMA_S_CTRL_AUX   (0xd00 + 0x10)
#define	DMA_S_BASEC_AUX(ch)
#define	DMA_S_LASTC_AUX(ch)
#define	DMA_S_STATC_AUX(ch)
#define	DMA_S_DONESTATD_AUX(d)
#define	DMA_S_DONESTATD_CLR_AUX(d)
#define	DMA_ARC_HS_GET_GROUP(handle)
#define	DMA_ARC_HS_GET_BIT_POS(handle)
#define	DMA_ARC_HS_BITMASK(handle)
#define	ARC_DMA_NP_ATTR   (1 << 3) /* Enable non posted writes */
#define	ARC_DMA_SET_DONE_ATTR   (1 << 0) /* Set done without triggering interrupt */
#define	ARC_DMA_INT_EN_ATTR   (1 << 1) /* Enable interrupt on completion */
#define	ARC_DMA_MAX_CHANNELS   16
#define	ARC_DMA_MAX_DESCRIPTORS   256
#define	ARC_DMA_CONFIGURED_CHANNELS   DT_INST_PROP(0, dma_channels)
#define	ARC_DMA_ATOMIC_WORDS   ATOMIC_BITMAP_SIZE(ARC_DMA_MAX_CHANNELS)
#define	CONFIGURE_ARC_DMA_IRQ(idx, inst)
#define	ARC_DMA_INIT(inst)

Enumerations
enum	arc_dma_channel_state {   ARC_DMA_FREE = 0 ,   ARC_DMA_IDLE ,   ARC_DMA_PREPARED ,   ARC_DMA_ACTIVE ,   ARC_DMA_SUSPENDED }

Functions
	LOG_MODULE_REGISTER (dma_arc, CONFIG_DMA_LOG_LEVEL)
static void	dma_arc_hs_config_hw (void)
static void	dma_arc_hs_init_channel_hw (uint32_t dma_ch, uint32_t base, uint32_t last)
static void	dma_arc_hs_start_hw (uint32_t dma_ch, const void *p_src, void *p_dst, uint32_t len, uint32_t attr)
static void	dma_arc_hs_next_hw (const void *p_src, void *p_dst, uint32_t len, uint32_t attr)
static uint32_t	dma_arc_hs_get_handle_hw (void)
static uint32_t	dma_arc_hs_poll_busy_hw (void)
static void	dma_arc_hs_clear_done_hw (uint32_t handle)
static uint32_t	dma_arc_hs_get_done_hw (uint32_t handle)
static int	dma_arc_hs_config (const struct device *dev, uint32_t channel, struct dma_config *config)
static int	dma_arc_hs_start (const struct device *dev, uint32_t channel)
static int	dma_arc_hs_stop (const struct device *dev, uint32_t channel)
static size_t	dma_arc_hs_calc_linked_transfer_size (struct arc_dma_channel *chan, struct dma_block_config *block, uint32_t burst_len)
static void	dma_arc_hs_trigger_linked_channel (const struct device *dev, struct arc_dma_data *data, struct arc_dma_channel *triggering_chan, uint32_t linked_ch_id)
static int	dma_arc_hs_status_poll (const struct device *dev, struct arc_dma_channel *chan, struct dma_status *stat)
static int	dma_arc_hs_get_status (const struct device *dev, uint32_t channel, struct dma_status *stat)
static int	dma_arc_hs_get_attribute (const struct device *dev, uint32_t type, uint32_t *value)
int	dma_arc_hs_transfer (const struct device *dev, uint32_t channel, const void *src, void *dst, size_t len, k_timeout_t timeout)
	Blocking memory-to-memory transfer using ARC HS DMA.
static void	dma_arc_hs_check_completion (const struct device *dev, uint32_t channel)
static void	dma_arc_hs_completion_work_handler (struct k_work *work)
static int	dma_arc_hs_init (const struct device *dev)

Variables
static const struct dma_driver_api	dma_arc_hs_api

Macro Definition Documentation

ARC_DMA_ATOMIC_WORDS

#define ARC_DMA_ATOMIC_WORDS   ATOMIC_BITMAP_SIZE(ARC_DMA_MAX_CHANNELS)

ARC_DMA_CONFIGURED_CHANNELS

#define ARC_DMA_CONFIGURED_CHANNELS   DT_INST_PROP(0, dma_channels)

ARC_DMA_INIT

#define ARC_DMA_INIT

(

inst

)

ARC_DMA_INT_EN_ATTR

#define ARC_DMA_INT_EN_ATTR   (1 << 1) /* Enable interrupt on completion */

ARC_DMA_MAX_CHANNELS

#define ARC_DMA_MAX_CHANNELS   16

ARC_DMA_MAX_DESCRIPTORS

#define ARC_DMA_MAX_DESCRIPTORS   256

ARC_DMA_NP_ATTR

#define ARC_DMA_NP_ATTR   (1 << 3) /* Enable non posted writes */

ARC_DMA_SET_DONE_ATTR

#define ARC_DMA_SET_DONE_ATTR   (1 << 0) /* Set done without triggering interrupt */

CONFIGURE_ARC_DMA_IRQ

#define CONFIGURE_ARC_DMA_IRQ	(		idx,
			inst )

Value:

        IF_ENABLED(DT_INST_IRQ_HAS_IDX(inst, idx), ( \
                IRQ_CONNECT(DT_INST_IRQ_BY_IDX(inst, idx, irq), \
                            DT_INST_IRQ_BY_IDX(inst, idx, priority), \
                            dma_arc_hs_isr, \
                            DEVICE_DT_INST_GET(inst), 0); \
                irq_enable(DT_INST_IRQ_BY_IDX(inst, idx, irq)); \
        ))

dma_addr_t

#define dma_addr_t   uint32_t

DMA_ARC_HS_BITMASK

#define DMA_ARC_HS_BITMASK

(

handle

)

Value:

        (1U << DMA_ARC_HS_GET_BIT_POS(handle)) /* Set bit at position                              \
                                                */

DMA_ARC_HS_GET_BIT_POS

#define DMA_ARC_HS_GET_BIT_POS

(

handle

)

Value:

((handle) & 0x1f) /* Extract bit position (lower 5 bits) */

DMA_ARC_HS_GET_GROUP

#define DMA_ARC_HS_GET_GROUP

(

handle

)

Value:

((handle) >> 5)   /* Extract group index (upper bits) */

DMA_AUX_BASE

#define DMA_AUX_BASE   (0xd00)

DMA_C_ATTR_AUX

#define DMA_C_ATTR_AUX   (0xd00 + 0x6)

DMA_C_CHAN_AUX

#define DMA_C_CHAN_AUX   (0xd00 + 0x1)

DMA_C_CTRL_AUX

#define DMA_C_CTRL_AUX   (0xd00 + 0x0)

DMA_C_DST_AUX

#define DMA_C_DST_AUX   (0xd00 + 0x4)

DMA_C_DST_HI_AUX

#define DMA_C_DST_HI_AUX   (0xd00 + 0x5)

DMA_C_HANDLE_AUX

#define DMA_C_HANDLE_AUX   (0xd00 + 0x8)

DMA_C_INTSTAT_AUX

#define DMA_C_INTSTAT_AUX   (0xd00 + 0xd)

DMA_C_INTSTAT_BUS_ERR

#define DMA_C_INTSTAT_BUS_ERR   (1 << 1) /* B: Bus error */

DMA_C_INTSTAT_CLR_AUX

#define DMA_C_INTSTAT_CLR_AUX   (0xd00 + 0xe)

DMA_C_INTSTAT_DONE

#define DMA_C_INTSTAT_DONE   (1 << 0) /* D: Transfer complete */

DMA_C_INTSTAT_OVERFLOW

#define DMA_C_INTSTAT_OVERFLOW   (1 << 2) /* O: Channel overflow */

DMA_C_LEN_AUX

#define DMA_C_LEN_AUX   (0xd00 + 0x7)

DMA_C_SRC_AUX

#define DMA_C_SRC_AUX   (0xd00 + 0x2)

DMA_C_SRC_HI_AUX

#define DMA_C_SRC_HI_AUX   (0xd00 + 0x3)

DMA_C_STAT_AUX

#define DMA_C_STAT_AUX   (0xd00 + 0xc)

DMA_S_BASEC_AUX

#define DMA_S_BASEC_AUX

(

ch

)

Value:

(0xd00 + 0x83 + ((ch) * 8))

DMA_S_CTRL_AUX

#define DMA_S_CTRL_AUX   (0xd00 + 0x10)

DMA_S_DONESTATD_AUX

#define DMA_S_DONESTATD_AUX

(

d

)

Value:

        (0xd00 + 0x20 + (d)) /* Descriptor selection. Each D stores descriptors d*32 +: 32 */

DMA_S_DONESTATD_CLR_AUX

#define DMA_S_DONESTATD_CLR_AUX

(

d

)

Value:

(0xd00 + 0x40 + (d))

DMA_S_LASTC_AUX

#define DMA_S_LASTC_AUX

(

ch

)

Value:

(0xd00 + 0x84 + ((ch) * 8))

DMA_S_STATC_AUX

#define DMA_S_STATC_AUX

(

ch

)

Value:

(0xd00 + 0x86 + ((ch) * 8))

DT_DRV_COMPAT

#define DT_DRV_COMPAT   snps_designware_dma_arc_hs

Enumeration Type Documentation

arc_dma_channel_state

enum arc_dma_channel_state

Enumerator
ARC_DMA_FREE	0
ARC_DMA_IDLE
ARC_DMA_PREPARED
ARC_DMA_ACTIVE
ARC_DMA_SUSPENDED

Function Documentation

dma_arc_hs_calc_linked_transfer_size()

size_t dma_arc_hs_calc_linked_transfer_size ( struct arc_dma_channel * chan, struct dma_block_config * block, uint32_t burst_len )

static

dma_arc_hs_check_completion()

void dma_arc_hs_check_completion ( const struct device * dev, uint32_t channel )

static

dma_arc_hs_clear_done_hw()

void dma_arc_hs_clear_done_hw ( uint32_t handle )

static

dma_arc_hs_completion_work_handler()

void dma_arc_hs_completion_work_handler ( struct k_work * work )

static

dma_arc_hs_config()

int dma_arc_hs_config ( const struct device * dev, uint32_t channel, struct dma_config * config )

static

dma_arc_hs_config_hw()

void dma_arc_hs_config_hw ( void )

static

dma_arc_hs_get_attribute()

int dma_arc_hs_get_attribute ( const struct device * dev, uint32_t type, uint32_t * value )

static

dma_arc_hs_get_done_hw()

uint32_t dma_arc_hs_get_done_hw ( uint32_t handle )

static

dma_arc_hs_get_handle_hw()

uint32_t dma_arc_hs_get_handle_hw ( void )

static

dma_arc_hs_get_status()

int dma_arc_hs_get_status ( const struct device * dev, uint32_t channel, struct dma_status * stat )

static

dma_arc_hs_init()

int dma_arc_hs_init ( const struct device * dev )

static

dma_arc_hs_init_channel_hw()

void dma_arc_hs_init_channel_hw ( uint32_t dma_ch, uint32_t base, uint32_t last )

static

dma_arc_hs_next_hw()

void dma_arc_hs_next_hw ( const void * p_src, void * p_dst, uint32_t len, uint32_t attr )

static

dma_arc_hs_poll_busy_hw()

uint32_t dma_arc_hs_poll_busy_hw ( void )

inlinestatic

dma_arc_hs_start()

int dma_arc_hs_start ( const struct device * dev, uint32_t channel )

static

dma_arc_hs_start_hw()

void dma_arc_hs_start_hw ( uint32_t dma_ch, const void * p_src, void * p_dst, uint32_t len, uint32_t attr )

static

dma_arc_hs_status_poll()

int dma_arc_hs_status_poll ( const struct device * dev, struct arc_dma_channel * chan, struct dma_status * stat )

static

dma_arc_hs_stop()

int dma_arc_hs_stop ( const struct device * dev, uint32_t channel )

static

dma_arc_hs_transfer()

int dma_arc_hs_transfer	(	const struct device *	dev,
		uint32_t	channel,
		const void *	src,
		void *	dst,
		size_t	len,
		k_timeout_t	timeout )

Blocking memory-to-memory transfer using ARC HS DMA.

Parameters

dev	DMA device (from DEVICE_DT_GET)
channel	DMA channel (0 to N-1)
src	Source address (4-byte aligned)
dst	Destination address (4-byte aligned)
len	Transfer length in bytes
timeout	Timeout for the transfer

Returns

0 on success, negative errno on error

dma_arc_hs_trigger_linked_channel()

void dma_arc_hs_trigger_linked_channel ( const struct device * dev, struct arc_dma_data * data, struct arc_dma_channel * triggering_chan, uint32_t linked_ch_id )

static

LOG_MODULE_REGISTER()

LOG_MODULE_REGISTER	(	dma_arc	,
		CONFIG_DMA_LOG_LEVEL	)

Variable Documentation

dma_arc_hs_api

const struct dma_driver_api dma_arc_hs_api

static

Initial value:

= {
        .config = dma_arc_hs_config,
        .start = dma_arc_hs_start,
        .stop = dma_arc_hs_stop,
        .suspend = NULL,
        .resume = NULL,
        .get_status = dma_arc_hs_get_status,
        .get_attribute = dma_arc_hs_get_attribute,
        .chan_filter = NULL,
        .chan_release = NULL,
}