TT Zephyr Platforms 19.0.0-rc2
Tenstorrent Firmware
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dw_apb_i2c.c File Reference
#include <zephyr/drivers/i2c.h>
#include <string.h>
#include "timer.h"
#include "dw_apb_i2c.h"
#include "asic_state.h"
#include "reg.h"
#include "util.h"

Data Structures

struct  DW_APB_I2C_IC_CON_reg_t
union  DW_APB_I2C_IC_CON_reg_u
struct  DW_APB_I2C_IC_RAW_INTR_STAT_reg_t
union  DW_APB_I2C_IC_RAW_INTR_STAT_reg_u

Macros

#define DW_APB_I2C_REG_MAP_BASE_ADDR   0x80060000
#define DW_APB_I2C1_REG_MAP_BASE_ADDR   0x80090000
#define DW_APB_I2C2_REG_MAP_BASE_ADDR   0x800A0000
#define RESET_UNIT_I2C_PAD_CNTL_REG_ADDR   0x800301C0
#define RESET_UNIT_I2C1_PAD_CNTL_REG_ADDR   0x800305CC
#define RESET_UNIT_I2C2_PAD_CNTL_REG_ADDR   0x800305D8
#define RESET_UNIT_I2C_PAD_DATA_REG_ADDR   0x800301C4
#define RESET_UNIT_I2C1_PAD_DATA_REG_ADDR   0x800305D0
#define RESET_UNIT_I2C2_PAD_DATA_REG_ADDR   0x800305DC
#define RESET_UNIT_I2C_CNTL_REG_ADDR   0x800300F0
#define DW_APB_I2C_IC_CON_REG_OFFSET   0x00000000
#define DW_APB_I2C_IC_STATUS_REG_OFFSET   0x00000070
#define DW_APB_I2C_IC_DATA_CMD_REG_OFFSET   0x00000010
#define DW_APB_I2C_IC_TX_ABRT_SOURCE_REG_OFFSET   0x00000080
#define DW_APB_I2C_IC_CLR_TX_ABRT_REG_OFFSET   0x00000054
#define DW_APB_I2C_IC_SMBUS_THIGH_MAX_IDLE_COUNT_REG_OFFSET   0x000000C4
#define DW_APB_I2C_IC_TAR_REG_OFFSET   0x00000004
#define DW_APB_I2C_IC_ENABLE_REG_OFFSET   0x0000006C
#define DW_APB_I2C_IC_SAR_REG_OFFSET   0x00000008
#define DW_APB_I2C_IC_SS_SCL_HCNT_REG_OFFSET   0x00000014
#define DW_APB_I2C_IC_SS_SCL_LCNT_REG_OFFSET   0x00000018
#define DW_APB_I2C_IC_FS_SPKLEN_REG_OFFSET   0x000000A0
#define DW_APB_I2C_IC_SDA_HOLD_REG_OFFSET   0x0000007C
#define DW_APB_I2C_IC_FS_SCL_HCNT_REG_OFFSET   0x0000001C
#define DW_APB_I2C_IC_FS_SCL_LCNT_REG_OFFSET   0x00000020
#define DW_APB_I2C_IC_RAW_INTR_STAT_REG_OFFSET   0x00000034
#define DW_APB_I2C_IC_CLR_RX_OVER_REG_OFFSET   0x00000048
#define DW_APB_I2C_IC_CLR_RD_REQ_REG_OFFSET   0x00000050
#define DW_APB_I2C_IC_CLR_STOP_DET_REG_OFFSET   0x00000060
#define DW_APB_I2C_IC_CON_MASTER_MODE_MASK   0x1
#define DW_APB_I2C_IC_STATUS_TFE_MASK   0x4
#define DW_APB_I2C_IC_STATUS_TFNF_MASK   0x2
#define DW_APB_I2C_IC_STATUS_RFNE_MASK   0x8
#define RESET_UNIT_I2C_PAD_CTRL_TRIEN_SCL_MASK   0x1
#define RESET_UNIT_I2C_PAD_CTRL_TRIEN_SDA_MASK   0x2
#define RESET_UNIT_I2C_PAD_CNTL_PUEN_MASK   0xC
#define RESET_UNIT_I2C_PAD_CNTL_RXEN_MASK   0xC0
#define DW_APB_I2C_IC_STATUS_MST_ACTIVITY_MASK   0x20
#define RESET_UNIT_I2C_PAD_CNTL_TRIEN_MASK   0x3
#define RESET_UNIT_I2C_CNTL_RESET_MASK   0x10
#define DW_APB_I2C_IC_TAR_IC_TAR_MASK   0x3FF
#define DW_APB_I2C_IC_SAR_IC_SAR_MASK   0x3FF
#define DW_APB_I2C_IC_CON_IC_RESTART_EN_MASK   0x20
#define DW_APB_I2C_IC_CON_IC_SLAVE_DISABLE_MASK   0x40
#define DW_APB_I2C_IC_CON_SPEED_SHIFT   1
#define DW_APB_I2C_IC_DATA_CMD_CMD_SHIFT   8
#define DW_APB_I2C_IC_DATA_CMD_STOP_SHIFT   9
#define RESET_UNIT_I2C_PAD_CNTL_DRV_SHIFT   10
#define IC_SS_SCL_HCNT_DEFAULT   200
#define IC_SS_SCL_LCNT_DEFAULT   235
#define IC_FS_SPKLEN_DEFAULT   3
#define IC_SDA_HOLD_DEFAULT   15
#define IC_FS_SCL_HCNT_DEFAULT   30
#define IC_FS_SCL_LCNT_DEFAULT   65
#define IC_TX_ABRT_SOURCE_MASK   0xFFFFF
#define IC_DATA_READ   (0x1 << DW_APB_I2C_IC_DATA_CMD_CMD_SHIFT)
#define IC_DATA_WRITE   (0x0 << DW_APB_I2C_IC_DATA_CMD_CMD_SHIFT)
#define IC_DATA_STOP   (0x1 << DW_APB_I2C_IC_DATA_CMD_STOP_SHIFT)
#define IC_DATA_RESTART   (0x1 << DW_APB_I2C_IC_DATA_CMD_RESTART_SHIFT)
#define IC_ABRT_A3_STATE   (0x1 << 21)
#define IC_VERIFY_FAIL   (0x1 << 22)
#define GET_I2C_OFFSET(REG_NAME)
#define DW_APB_I2C_IC_CON_REG_DEFAULT   (0x00000065)
#define DW_APB_I2C_IC_RAW_INTR_STAT_REG_DEFAULT   (0x00000000)

Functions

static uint32_t GetI2CBaseAddress (uint32_t id)
bool IsValidI2CMasterId (uint32_t id)
static uint32_t GetI2CRegAddr (uint32_t id, uint32_t offset)
static uint32_t GetI2CPadCntlAddr (uint32_t id)
static uint32_t GetI2CPadDataAddr (uint32_t id)
void I2CRecoverBus (uint32_t id)
static void WaitTxFifoEmpty (uint32_t id)
static void WaitTxFifoNotFull (uint32_t id)
static void WaitMasterIdle (uint32_t id)
static void WriteTxFifo (uint32_t id, uint32_t data)
static uint32_t CheckTxAbrt (uint32_t id)
static uint32_t WaitAllTxDone (uint32_t id)
uint32_t I2CReadRxFifo (uint32_t id, uint8_t *p_read_buf)
void I2CInitGPIO (uint32_t id)
void I2CInit (I2CMode mode, uint32_t slave_addr, I2CSpeedMode speed, uint32_t id)
void I2CReset (void)
uint32_t I2CTransaction (uint32_t id, const uint8_t *write_data, uint32_t write_len, uint8_t *read_data, uint32_t read_len)
uint32_t I2CWriteBytes (uint32_t id, uint16_t command, uint32_t command_byte_size, const uint8_t *p_write_buf, uint32_t data_byte_size)
uint32_t I2CReadBytes (uint32_t id, uint16_t command, uint32_t command_byte_size, uint8_t *p_read_buf, uint32_t data_byte_size, uint8_t flip_bytes)
uint32_t I2CRMWV (uint32_t id, uint16_t command, uint32_t command_byte_size, const uint8_t *p_data, const uint8_t *p_mask, uint32_t data_byte_size)
 I2C Read-Modify-Write-Verify.
void SetI2CSlaveCallbacks (uint32_t id, const struct i2c_target_callbacks *cb)
void PollI2CSlave (uint32_t id)

Variables

uint8_t asic_state
struct i2c_target_config i2c_target_config [3]

Macro Definition Documentation

◆ DW_APB_I2C1_REG_MAP_BASE_ADDR

#define DW_APB_I2C1_REG_MAP_BASE_ADDR   0x80090000

◆ DW_APB_I2C2_REG_MAP_BASE_ADDR

#define DW_APB_I2C2_REG_MAP_BASE_ADDR   0x800A0000

◆ DW_APB_I2C_IC_CLR_RD_REQ_REG_OFFSET

#define DW_APB_I2C_IC_CLR_RD_REQ_REG_OFFSET   0x00000050

◆ DW_APB_I2C_IC_CLR_RX_OVER_REG_OFFSET

#define DW_APB_I2C_IC_CLR_RX_OVER_REG_OFFSET   0x00000048

◆ DW_APB_I2C_IC_CLR_STOP_DET_REG_OFFSET

#define DW_APB_I2C_IC_CLR_STOP_DET_REG_OFFSET   0x00000060

◆ DW_APB_I2C_IC_CLR_TX_ABRT_REG_OFFSET

#define DW_APB_I2C_IC_CLR_TX_ABRT_REG_OFFSET   0x00000054

◆ DW_APB_I2C_IC_CON_IC_RESTART_EN_MASK

#define DW_APB_I2C_IC_CON_IC_RESTART_EN_MASK   0x20

◆ DW_APB_I2C_IC_CON_IC_SLAVE_DISABLE_MASK

#define DW_APB_I2C_IC_CON_IC_SLAVE_DISABLE_MASK   0x40

◆ DW_APB_I2C_IC_CON_MASTER_MODE_MASK

#define DW_APB_I2C_IC_CON_MASTER_MODE_MASK   0x1

◆ DW_APB_I2C_IC_CON_REG_DEFAULT

#define DW_APB_I2C_IC_CON_REG_DEFAULT   (0x00000065)

◆ DW_APB_I2C_IC_CON_REG_OFFSET

#define DW_APB_I2C_IC_CON_REG_OFFSET   0x00000000

◆ DW_APB_I2C_IC_CON_SPEED_SHIFT

#define DW_APB_I2C_IC_CON_SPEED_SHIFT   1

◆ DW_APB_I2C_IC_DATA_CMD_CMD_SHIFT

#define DW_APB_I2C_IC_DATA_CMD_CMD_SHIFT   8

◆ DW_APB_I2C_IC_DATA_CMD_REG_OFFSET

#define DW_APB_I2C_IC_DATA_CMD_REG_OFFSET   0x00000010

◆ DW_APB_I2C_IC_DATA_CMD_STOP_SHIFT

#define DW_APB_I2C_IC_DATA_CMD_STOP_SHIFT   9

◆ DW_APB_I2C_IC_ENABLE_REG_OFFSET

#define DW_APB_I2C_IC_ENABLE_REG_OFFSET   0x0000006C

◆ DW_APB_I2C_IC_FS_SCL_HCNT_REG_OFFSET

#define DW_APB_I2C_IC_FS_SCL_HCNT_REG_OFFSET   0x0000001C

◆ DW_APB_I2C_IC_FS_SCL_LCNT_REG_OFFSET

#define DW_APB_I2C_IC_FS_SCL_LCNT_REG_OFFSET   0x00000020

◆ DW_APB_I2C_IC_FS_SPKLEN_REG_OFFSET

#define DW_APB_I2C_IC_FS_SPKLEN_REG_OFFSET   0x000000A0

◆ DW_APB_I2C_IC_RAW_INTR_STAT_REG_DEFAULT

#define DW_APB_I2C_IC_RAW_INTR_STAT_REG_DEFAULT   (0x00000000)

◆ DW_APB_I2C_IC_RAW_INTR_STAT_REG_OFFSET

#define DW_APB_I2C_IC_RAW_INTR_STAT_REG_OFFSET   0x00000034

◆ DW_APB_I2C_IC_SAR_IC_SAR_MASK

#define DW_APB_I2C_IC_SAR_IC_SAR_MASK   0x3FF

◆ DW_APB_I2C_IC_SAR_REG_OFFSET

#define DW_APB_I2C_IC_SAR_REG_OFFSET   0x00000008

◆ DW_APB_I2C_IC_SDA_HOLD_REG_OFFSET

#define DW_APB_I2C_IC_SDA_HOLD_REG_OFFSET   0x0000007C

◆ DW_APB_I2C_IC_SMBUS_THIGH_MAX_IDLE_COUNT_REG_OFFSET

#define DW_APB_I2C_IC_SMBUS_THIGH_MAX_IDLE_COUNT_REG_OFFSET   0x000000C4

◆ DW_APB_I2C_IC_SS_SCL_HCNT_REG_OFFSET

#define DW_APB_I2C_IC_SS_SCL_HCNT_REG_OFFSET   0x00000014

◆ DW_APB_I2C_IC_SS_SCL_LCNT_REG_OFFSET

#define DW_APB_I2C_IC_SS_SCL_LCNT_REG_OFFSET   0x00000018

◆ DW_APB_I2C_IC_STATUS_MST_ACTIVITY_MASK

#define DW_APB_I2C_IC_STATUS_MST_ACTIVITY_MASK   0x20

◆ DW_APB_I2C_IC_STATUS_REG_OFFSET

#define DW_APB_I2C_IC_STATUS_REG_OFFSET   0x00000070

◆ DW_APB_I2C_IC_STATUS_RFNE_MASK

#define DW_APB_I2C_IC_STATUS_RFNE_MASK   0x8

◆ DW_APB_I2C_IC_STATUS_TFE_MASK

#define DW_APB_I2C_IC_STATUS_TFE_MASK   0x4

◆ DW_APB_I2C_IC_STATUS_TFNF_MASK

#define DW_APB_I2C_IC_STATUS_TFNF_MASK   0x2

◆ DW_APB_I2C_IC_TAR_IC_TAR_MASK

#define DW_APB_I2C_IC_TAR_IC_TAR_MASK   0x3FF

◆ DW_APB_I2C_IC_TAR_REG_OFFSET

#define DW_APB_I2C_IC_TAR_REG_OFFSET   0x00000004

◆ DW_APB_I2C_IC_TX_ABRT_SOURCE_REG_OFFSET

#define DW_APB_I2C_IC_TX_ABRT_SOURCE_REG_OFFSET   0x00000080

◆ DW_APB_I2C_REG_MAP_BASE_ADDR

#define DW_APB_I2C_REG_MAP_BASE_ADDR   0x80060000

◆ GET_I2C_OFFSET

#define GET_I2C_OFFSET ( REG_NAME)
Value:
DW_APB_I2C_##REG_NAME##_REG_OFFSET

◆ IC_ABRT_A3_STATE

#define IC_ABRT_A3_STATE   (0x1 << 21)

◆ IC_DATA_READ

#define IC_DATA_READ   (0x1 << DW_APB_I2C_IC_DATA_CMD_CMD_SHIFT)

◆ IC_DATA_RESTART

#define IC_DATA_RESTART   (0x1 << DW_APB_I2C_IC_DATA_CMD_RESTART_SHIFT)

◆ IC_DATA_STOP

#define IC_DATA_STOP   (0x1 << DW_APB_I2C_IC_DATA_CMD_STOP_SHIFT)

◆ IC_DATA_WRITE

#define IC_DATA_WRITE   (0x0 << DW_APB_I2C_IC_DATA_CMD_CMD_SHIFT)

◆ IC_FS_SCL_HCNT_DEFAULT

#define IC_FS_SCL_HCNT_DEFAULT   30

◆ IC_FS_SCL_LCNT_DEFAULT

#define IC_FS_SCL_LCNT_DEFAULT   65

◆ IC_FS_SPKLEN_DEFAULT

#define IC_FS_SPKLEN_DEFAULT   3

◆ IC_SDA_HOLD_DEFAULT

#define IC_SDA_HOLD_DEFAULT   15

◆ IC_SS_SCL_HCNT_DEFAULT

#define IC_SS_SCL_HCNT_DEFAULT   200

◆ IC_SS_SCL_LCNT_DEFAULT

#define IC_SS_SCL_LCNT_DEFAULT   235

◆ IC_TX_ABRT_SOURCE_MASK

#define IC_TX_ABRT_SOURCE_MASK   0xFFFFF

◆ IC_VERIFY_FAIL

#define IC_VERIFY_FAIL   (0x1 << 22)

◆ RESET_UNIT_I2C1_PAD_CNTL_REG_ADDR

#define RESET_UNIT_I2C1_PAD_CNTL_REG_ADDR   0x800305CC

◆ RESET_UNIT_I2C1_PAD_DATA_REG_ADDR

#define RESET_UNIT_I2C1_PAD_DATA_REG_ADDR   0x800305D0

◆ RESET_UNIT_I2C2_PAD_CNTL_REG_ADDR

#define RESET_UNIT_I2C2_PAD_CNTL_REG_ADDR   0x800305D8

◆ RESET_UNIT_I2C2_PAD_DATA_REG_ADDR

#define RESET_UNIT_I2C2_PAD_DATA_REG_ADDR   0x800305DC

◆ RESET_UNIT_I2C_CNTL_REG_ADDR

#define RESET_UNIT_I2C_CNTL_REG_ADDR   0x800300F0

◆ RESET_UNIT_I2C_CNTL_RESET_MASK

#define RESET_UNIT_I2C_CNTL_RESET_MASK   0x10

◆ RESET_UNIT_I2C_PAD_CNTL_DRV_SHIFT

#define RESET_UNIT_I2C_PAD_CNTL_DRV_SHIFT   10

◆ RESET_UNIT_I2C_PAD_CNTL_PUEN_MASK

#define RESET_UNIT_I2C_PAD_CNTL_PUEN_MASK   0xC

◆ RESET_UNIT_I2C_PAD_CNTL_REG_ADDR

#define RESET_UNIT_I2C_PAD_CNTL_REG_ADDR   0x800301C0

◆ RESET_UNIT_I2C_PAD_CNTL_RXEN_MASK

#define RESET_UNIT_I2C_PAD_CNTL_RXEN_MASK   0xC0

◆ RESET_UNIT_I2C_PAD_CNTL_TRIEN_MASK

#define RESET_UNIT_I2C_PAD_CNTL_TRIEN_MASK   0x3

◆ RESET_UNIT_I2C_PAD_CTRL_TRIEN_SCL_MASK

#define RESET_UNIT_I2C_PAD_CTRL_TRIEN_SCL_MASK   0x1

◆ RESET_UNIT_I2C_PAD_CTRL_TRIEN_SDA_MASK

#define RESET_UNIT_I2C_PAD_CTRL_TRIEN_SDA_MASK   0x2

◆ RESET_UNIT_I2C_PAD_DATA_REG_ADDR

#define RESET_UNIT_I2C_PAD_DATA_REG_ADDR   0x800301C4

Function Documentation

◆ CheckTxAbrt()

uint32_t CheckTxAbrt ( uint32_t id)
static

◆ GetI2CBaseAddress()

uint32_t GetI2CBaseAddress ( uint32_t id)
inlinestatic

◆ GetI2CPadCntlAddr()

uint32_t GetI2CPadCntlAddr ( uint32_t id)
inlinestatic

◆ GetI2CPadDataAddr()

uint32_t GetI2CPadDataAddr ( uint32_t id)
inlinestatic

◆ GetI2CRegAddr()

uint32_t GetI2CRegAddr ( uint32_t id,
uint32_t offset )
inlinestatic

◆ I2CInit()

void I2CInit ( I2CMode mode,
uint32_t slave_addr,
I2CSpeedMode speed,
uint32_t id )

◆ I2CInitGPIO()

void I2CInitGPIO ( uint32_t id)

◆ I2CReadBytes()

uint32_t I2CReadBytes ( uint32_t id,
uint16_t command,
uint32_t command_byte_size,
uint8_t * p_read_buf,
uint32_t data_byte_size,
uint8_t flip_bytes )

◆ I2CReadRxFifo()

uint32_t I2CReadRxFifo ( uint32_t id,
uint8_t * p_read_buf )

◆ I2CRecoverBus()

void I2CRecoverBus ( uint32_t id)

◆ I2CReset()

void I2CReset ( void )

◆ I2CRMWV()

uint32_t I2CRMWV ( uint32_t id,
uint16_t command,
uint32_t command_byte_size,
const uint8_t * p_data,
const uint8_t * p_mask,
uint32_t data_byte_size )

I2C Read-Modify-Write-Verify.

◆ I2CTransaction()

uint32_t I2CTransaction ( uint32_t id,
const uint8_t * write_data,
uint32_t write_len,
uint8_t * read_data,
uint32_t read_len )

◆ I2CWriteBytes()

uint32_t I2CWriteBytes ( uint32_t id,
uint16_t command,
uint32_t command_byte_size,
const uint8_t * p_write_buf,
uint32_t data_byte_size )

◆ IsValidI2CMasterId()

bool IsValidI2CMasterId ( uint32_t id)

◆ PollI2CSlave()

void PollI2CSlave ( uint32_t id)

◆ SetI2CSlaveCallbacks()

void SetI2CSlaveCallbacks ( uint32_t id,
const struct i2c_target_callbacks * cb )

◆ WaitAllTxDone()

uint32_t WaitAllTxDone ( uint32_t id)
static

◆ WaitMasterIdle()

void WaitMasterIdle ( uint32_t id)
static

◆ WaitTxFifoEmpty()

void WaitTxFifoEmpty ( uint32_t id)
static

◆ WaitTxFifoNotFull()

void WaitTxFifoNotFull ( uint32_t id)
static

◆ WriteTxFifo()

void WriteTxFifo ( uint32_t id,
uint32_t data )
static

Variable Documentation

◆ asic_state

uint8_t asic_state
extern

◆ i2c_target_config

struct i2c_target_config i2c_target_config[3]