TT Zephyr Platforms 18.11.99
Tenstorrent Firmware
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functional_efuse.h File Reference
#include <stdint.h>
#include <zephyr/sys/util.h>

Go to the source code of this file.

Macros

#define FUSE_ASIC_ID_OLD_START_BIT   1056
#define FUSE_ASIC_ID_OLD_END_BIT   1071
#define FUSE_ASIC_ID_LOW_START_BIT   1600
#define FUSE_ASIC_ID_LOW_END_BIT   1631
#define FUSE_ATE_TENSIX_ROW0_TEST_STATUS_START_BIT   3168
#define FUSE_ATE_TENSIX_ROW0_TEST_STATUS_END_BIT   3199
#define FUSE_ATE_TENSIX_ROW1_TEST_STATUS_START_BIT   3200
#define FUSE_ATE_TENSIX_ROW1_TEST_STATUS_END_BIT   3231
#define FUSE_ATE_TENSIX_ROW2_TEST_STATUS_START_BIT   3232
#define FUSE_ATE_TENSIX_ROW2_TEST_STATUS_END_BIT   3263
#define FUSE_ATE_TENSIX_ROW3_TEST_STATUS_START_BIT   3264
#define FUSE_ATE_TENSIX_ROW3_TEST_STATUS_END_BIT   3295
#define FUSE_ATE_TENSIX_ROW4_TEST_STATUS_START_BIT   3296
#define FUSE_ATE_TENSIX_ROW4_TEST_STATUS_END_BIT   3327
#define FUSE_ATE_TENSIX_ROW5_TEST_STATUS_START_BIT   3328
#define FUSE_ATE_TENSIX_ROW5_TEST_STATUS_END_BIT   3359
#define FUSE_ATE_TENSIX_ROW6_TEST_STATUS_START_BIT   3360
#define FUSE_ATE_TENSIX_ROW6_TEST_STATUS_END_BIT   3391
#define FUSE_ATE_TENSIX_ROW7_TEST_STATUS_START_BIT   3392
#define FUSE_ATE_TENSIX_ROW7_TEST_STATUS_END_BIT   3423
#define FUSE_ATE_TENSIX_ROW8_TEST_STATUS_START_BIT   3424
#define FUSE_ATE_TENSIX_ROW8_TEST_STATUS_END_BIT   3455
#define FUSE_ATE_TENSIX_ROW9_TEST_STATUS_START_BIT   3456
#define FUSE_ATE_TENSIX_ROW9_TEST_STATUS_END_BIT   3487
#define FUSE_ATE_SERDES_PHY_TEST_STATUS_START_BIT   3488
#define FUSE_ATE_SERDES_PHY_TEST_STATUS_END_BIT   3503
#define FUSE_ATE_DDR_TEST_STATUS_START_BIT   3504
#define FUSE_ATE_DDR_TEST_STATUS_END_BIT   3511
#define FUSE_ATE_PCIE_SPEED_TEST_START_BIT   3512
#define FUSE_ATE_PCIE_SPEED_TEST_END_BIT   3515
#define FUSE_ATE_AT_SPEED_AICLK_TEST_STATUS_START_BIT   3516
#define FUSE_ATE_AT_SPEED_AICLK_TEST_STATUS_END_BIT   3519
#define FUSE_ATE_RISCV_L2_TEST_STATUS_START_BIT   3520
#define FUSE_ATE_RISCV_L2_TEST_STATUS_END_BIT   3535
#define FUSE_ATE_ETH_CTRL_TEST_STATUS_START_BIT   3536
#define FUSE_ATE_ETH_CTRL_TEST_STATUS_END_BIT   3551
#define FUSE_SLT_ATE_SLT_STATUS_START_BIT   4160
#define FUSE_SLT_ATE_SLT_STATUS_END_BIT   4161
#define FUSE_SLT_FUSE_MAP_VERSION_START_BIT   4162
#define FUSE_SLT_FUSE_MAP_VERSION_END_BIT   4191
#define FUSE_SLT_SLT_BINNING_START_BIT   4192
#define FUSE_SLT_SLT_BINNING_END_BIT   4223
#define FUSE_SLT_DDR_TEST_STATUS_16G_START_BIT   5472
#define FUSE_SLT_DDR_TEST_STATUS_16G_END_BIT   5479
#define FUSE_SLT_DDR_TEST_STATUS_14G_START_BIT   5480
#define FUSE_SLT_DDR_TEST_STATUS_14G_END_BIT   5487
#define FUSE_SLT_DDR_TEST_STATUS_12G_START_BIT   5488
#define FUSE_SLT_DDR_TEST_STATUS_12G_END_BIT   5495
#define FUSE_SLT_PCIE_SPEED_TEST_START_BIT   5496
#define FUSE_SLT_PCIE_SPEED_TEST_END_BIT   5499
#define FUSE_SLT_SLT_SPEED_TEST_START_BIT   5500
#define FUSE_SLT_SLT_SPEED_TEST_END_BIT   5503
#define FUSE_SLT_RISCV_L2_TEST_STATUS_START_BIT   5504
#define FUSE_SLT_RISCV_L2_TEST_STATUS_END_BIT   5519
#define FUSE_SLT_ETH_CTRL_TEST_STATUS_START_BIT   5520
#define FUSE_SLT_ETH_CTRL_TEST_STATUS_END_BIT   5535
#define FUSE_SLT_HARVESTED_TENSIX_COLUMNS_START_BIT   5536
#define FUSE_SLT_HARVESTED_TENSIX_COLUMNS_END_BIT   5551
#define FUSE_ASIC_ID_HIGH_START_BIT   5568
#define FUSE_ASIC_ID_HIGH_END_BIT   5599
#define READ_FUNCTIONAL_EFUSE(fuse_name)

Functions

uint32_t ReadFunctionalEfuse (uint32_t start_bit, uint32_t end_bit)

Macro Definition Documentation

◆ FUSE_ASIC_ID_HIGH_END_BIT

#define FUSE_ASIC_ID_HIGH_END_BIT   5599

◆ FUSE_ASIC_ID_HIGH_START_BIT

#define FUSE_ASIC_ID_HIGH_START_BIT   5568

◆ FUSE_ASIC_ID_LOW_END_BIT

#define FUSE_ASIC_ID_LOW_END_BIT   1631

◆ FUSE_ASIC_ID_LOW_START_BIT

#define FUSE_ASIC_ID_LOW_START_BIT   1600

◆ FUSE_ASIC_ID_OLD_END_BIT

#define FUSE_ASIC_ID_OLD_END_BIT   1071

◆ FUSE_ASIC_ID_OLD_START_BIT

#define FUSE_ASIC_ID_OLD_START_BIT   1056

◆ FUSE_ATE_AT_SPEED_AICLK_TEST_STATUS_END_BIT

#define FUSE_ATE_AT_SPEED_AICLK_TEST_STATUS_END_BIT   3519

◆ FUSE_ATE_AT_SPEED_AICLK_TEST_STATUS_START_BIT

#define FUSE_ATE_AT_SPEED_AICLK_TEST_STATUS_START_BIT   3516

◆ FUSE_ATE_DDR_TEST_STATUS_END_BIT

#define FUSE_ATE_DDR_TEST_STATUS_END_BIT   3511

◆ FUSE_ATE_DDR_TEST_STATUS_START_BIT

#define FUSE_ATE_DDR_TEST_STATUS_START_BIT   3504

◆ FUSE_ATE_ETH_CTRL_TEST_STATUS_END_BIT

#define FUSE_ATE_ETH_CTRL_TEST_STATUS_END_BIT   3551

◆ FUSE_ATE_ETH_CTRL_TEST_STATUS_START_BIT

#define FUSE_ATE_ETH_CTRL_TEST_STATUS_START_BIT   3536

◆ FUSE_ATE_PCIE_SPEED_TEST_END_BIT

#define FUSE_ATE_PCIE_SPEED_TEST_END_BIT   3515

◆ FUSE_ATE_PCIE_SPEED_TEST_START_BIT

#define FUSE_ATE_PCIE_SPEED_TEST_START_BIT   3512

◆ FUSE_ATE_RISCV_L2_TEST_STATUS_END_BIT

#define FUSE_ATE_RISCV_L2_TEST_STATUS_END_BIT   3535

◆ FUSE_ATE_RISCV_L2_TEST_STATUS_START_BIT

#define FUSE_ATE_RISCV_L2_TEST_STATUS_START_BIT   3520

◆ FUSE_ATE_SERDES_PHY_TEST_STATUS_END_BIT

#define FUSE_ATE_SERDES_PHY_TEST_STATUS_END_BIT   3503

◆ FUSE_ATE_SERDES_PHY_TEST_STATUS_START_BIT

#define FUSE_ATE_SERDES_PHY_TEST_STATUS_START_BIT   3488

◆ FUSE_ATE_TENSIX_ROW0_TEST_STATUS_END_BIT

#define FUSE_ATE_TENSIX_ROW0_TEST_STATUS_END_BIT   3199

◆ FUSE_ATE_TENSIX_ROW0_TEST_STATUS_START_BIT

#define FUSE_ATE_TENSIX_ROW0_TEST_STATUS_START_BIT   3168

◆ FUSE_ATE_TENSIX_ROW1_TEST_STATUS_END_BIT

#define FUSE_ATE_TENSIX_ROW1_TEST_STATUS_END_BIT   3231

◆ FUSE_ATE_TENSIX_ROW1_TEST_STATUS_START_BIT

#define FUSE_ATE_TENSIX_ROW1_TEST_STATUS_START_BIT   3200

◆ FUSE_ATE_TENSIX_ROW2_TEST_STATUS_END_BIT

#define FUSE_ATE_TENSIX_ROW2_TEST_STATUS_END_BIT   3263

◆ FUSE_ATE_TENSIX_ROW2_TEST_STATUS_START_BIT

#define FUSE_ATE_TENSIX_ROW2_TEST_STATUS_START_BIT   3232

◆ FUSE_ATE_TENSIX_ROW3_TEST_STATUS_END_BIT

#define FUSE_ATE_TENSIX_ROW3_TEST_STATUS_END_BIT   3295

◆ FUSE_ATE_TENSIX_ROW3_TEST_STATUS_START_BIT

#define FUSE_ATE_TENSIX_ROW3_TEST_STATUS_START_BIT   3264

◆ FUSE_ATE_TENSIX_ROW4_TEST_STATUS_END_BIT

#define FUSE_ATE_TENSIX_ROW4_TEST_STATUS_END_BIT   3327

◆ FUSE_ATE_TENSIX_ROW4_TEST_STATUS_START_BIT

#define FUSE_ATE_TENSIX_ROW4_TEST_STATUS_START_BIT   3296

◆ FUSE_ATE_TENSIX_ROW5_TEST_STATUS_END_BIT

#define FUSE_ATE_TENSIX_ROW5_TEST_STATUS_END_BIT   3359

◆ FUSE_ATE_TENSIX_ROW5_TEST_STATUS_START_BIT

#define FUSE_ATE_TENSIX_ROW5_TEST_STATUS_START_BIT   3328

◆ FUSE_ATE_TENSIX_ROW6_TEST_STATUS_END_BIT

#define FUSE_ATE_TENSIX_ROW6_TEST_STATUS_END_BIT   3391

◆ FUSE_ATE_TENSIX_ROW6_TEST_STATUS_START_BIT

#define FUSE_ATE_TENSIX_ROW6_TEST_STATUS_START_BIT   3360

◆ FUSE_ATE_TENSIX_ROW7_TEST_STATUS_END_BIT

#define FUSE_ATE_TENSIX_ROW7_TEST_STATUS_END_BIT   3423

◆ FUSE_ATE_TENSIX_ROW7_TEST_STATUS_START_BIT

#define FUSE_ATE_TENSIX_ROW7_TEST_STATUS_START_BIT   3392

◆ FUSE_ATE_TENSIX_ROW8_TEST_STATUS_END_BIT

#define FUSE_ATE_TENSIX_ROW8_TEST_STATUS_END_BIT   3455

◆ FUSE_ATE_TENSIX_ROW8_TEST_STATUS_START_BIT

#define FUSE_ATE_TENSIX_ROW8_TEST_STATUS_START_BIT   3424

◆ FUSE_ATE_TENSIX_ROW9_TEST_STATUS_END_BIT

#define FUSE_ATE_TENSIX_ROW9_TEST_STATUS_END_BIT   3487

◆ FUSE_ATE_TENSIX_ROW9_TEST_STATUS_START_BIT

#define FUSE_ATE_TENSIX_ROW9_TEST_STATUS_START_BIT   3456

◆ FUSE_SLT_ATE_SLT_STATUS_END_BIT

#define FUSE_SLT_ATE_SLT_STATUS_END_BIT   4161

◆ FUSE_SLT_ATE_SLT_STATUS_START_BIT

#define FUSE_SLT_ATE_SLT_STATUS_START_BIT   4160

◆ FUSE_SLT_DDR_TEST_STATUS_12G_END_BIT

#define FUSE_SLT_DDR_TEST_STATUS_12G_END_BIT   5495

◆ FUSE_SLT_DDR_TEST_STATUS_12G_START_BIT

#define FUSE_SLT_DDR_TEST_STATUS_12G_START_BIT   5488

◆ FUSE_SLT_DDR_TEST_STATUS_14G_END_BIT

#define FUSE_SLT_DDR_TEST_STATUS_14G_END_BIT   5487

◆ FUSE_SLT_DDR_TEST_STATUS_14G_START_BIT

#define FUSE_SLT_DDR_TEST_STATUS_14G_START_BIT   5480

◆ FUSE_SLT_DDR_TEST_STATUS_16G_END_BIT

#define FUSE_SLT_DDR_TEST_STATUS_16G_END_BIT   5479

◆ FUSE_SLT_DDR_TEST_STATUS_16G_START_BIT

#define FUSE_SLT_DDR_TEST_STATUS_16G_START_BIT   5472

◆ FUSE_SLT_ETH_CTRL_TEST_STATUS_END_BIT

#define FUSE_SLT_ETH_CTRL_TEST_STATUS_END_BIT   5535

◆ FUSE_SLT_ETH_CTRL_TEST_STATUS_START_BIT

#define FUSE_SLT_ETH_CTRL_TEST_STATUS_START_BIT   5520

◆ FUSE_SLT_FUSE_MAP_VERSION_END_BIT

#define FUSE_SLT_FUSE_MAP_VERSION_END_BIT   4191

◆ FUSE_SLT_FUSE_MAP_VERSION_START_BIT

#define FUSE_SLT_FUSE_MAP_VERSION_START_BIT   4162

◆ FUSE_SLT_HARVESTED_TENSIX_COLUMNS_END_BIT

#define FUSE_SLT_HARVESTED_TENSIX_COLUMNS_END_BIT   5551

◆ FUSE_SLT_HARVESTED_TENSIX_COLUMNS_START_BIT

#define FUSE_SLT_HARVESTED_TENSIX_COLUMNS_START_BIT   5536

◆ FUSE_SLT_PCIE_SPEED_TEST_END_BIT

#define FUSE_SLT_PCIE_SPEED_TEST_END_BIT   5499

◆ FUSE_SLT_PCIE_SPEED_TEST_START_BIT

#define FUSE_SLT_PCIE_SPEED_TEST_START_BIT   5496

◆ FUSE_SLT_RISCV_L2_TEST_STATUS_END_BIT

#define FUSE_SLT_RISCV_L2_TEST_STATUS_END_BIT   5519

◆ FUSE_SLT_RISCV_L2_TEST_STATUS_START_BIT

#define FUSE_SLT_RISCV_L2_TEST_STATUS_START_BIT   5504

◆ FUSE_SLT_SLT_BINNING_END_BIT

#define FUSE_SLT_SLT_BINNING_END_BIT   4223

◆ FUSE_SLT_SLT_BINNING_START_BIT

#define FUSE_SLT_SLT_BINNING_START_BIT   4192

◆ FUSE_SLT_SLT_SPEED_TEST_END_BIT

#define FUSE_SLT_SLT_SPEED_TEST_END_BIT   5503

◆ FUSE_SLT_SLT_SPEED_TEST_START_BIT

#define FUSE_SLT_SLT_SPEED_TEST_START_BIT   5500

◆ READ_FUNCTIONAL_EFUSE

#define READ_FUNCTIONAL_EFUSE ( fuse_name)
Value:
(ZERO_OR_COMPILE_ERROR(FUSE_##fuse_name##_END_BIT > FUSE_##fuse_name##_START_BIT) + \
ZERO_OR_COMPILE_ERROR(FUSE_##fuse_name##_END_BIT - FUSE_##fuse_name##_START_BIT < 32) + \
ReadFunctionalEfuse(FUSE_##fuse_name##_START_BIT, FUSE_##fuse_name##_END_BIT))
#define ZERO_OR_COMPILE_ERROR(cond)

Function Documentation

◆ ReadFunctionalEfuse()

uint32_t ReadFunctionalEfuse ( uint32_t start_bit,
uint32_t end_bit )