TT Zephyr Platforms 18.11.99
Tenstorrent Firmware
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gddr.h
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1/*
2 * Copyright (c) 2024 Tenstorrent AI ULC
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6#ifndef _GDDR_H_
7#define _GDDR_H_
8
10
11#include <zephyr/sys_clock.h>
12
13#define MIN_GDDR_SPEED 12000
14#define MAX_GDDR_SPEED 20000
15#define GDDR_SPEED_TO_MEMCLK_RATIO 16
16#define NUM_GDDR 8
17#define NUM_MRISC_NOC2AXI_PORT 3
18
19/* MRISC FW telemetry base addr */
20#define GDDR_TELEMETRY_TABLE_ADDR 0x8000
21#define GDDR_MSG_STRUCT_ADDR 0x6000
22
23#define RISC_CTRL_A_SCRATCH_0__REG_ADDR 0xFFB14010
24#define RISC_CTRL_A_SCRATCH_1__REG_ADDR 0xFFB14014
25#define RISC_CTRL_A_SCRATCH_2__REG_ADDR 0xFFB14018
26#define MRISC_INIT_STATUS RISC_CTRL_A_SCRATCH_0__REG_ADDR
27#define MRISC_POST_CODE RISC_CTRL_A_SCRATCH_1__REG_ADDR
28#define MRISC_MSG_REGISTER RISC_CTRL_A_SCRATCH_2__REG_ADDR
29
30#define MRISC_INIT_FINISHED 0xdeadbeef
31#define MRISC_INIT_FAILED 0xfa11
32#define MRISC_INIT_BEFORE 0x11111111
33#define MRISC_INIT_STARTED 0x0
34#define MRISC_INIT_TIMEOUT 1000 /* In ms */
35#define MRISC_MEMTEST_TIMEOUT 1000 /* In ms */
36#define MRISC_POWER_SETTING_TIMEOUT_MS 1000
37
38/* Defined by MRISC FW */
39
43#define MRISC_MSG_TYPE_NONE 0
45#define MRISC_MSG_TYPE_PHY_POWERDOWN 1
47#define MRISC_MSG_TYPE_PHY_WAKEUP 2
49#define MRISC_MSG_TYPE_RUN_MEMTEST 8
50
51int read_gddr_telemetry_table(uint8_t gddr_inst, gddr_telemetry_table_t *gddr_telemetry);
52
59
60#endif
int read_gddr_telemetry_table(uint8_t gddr_inst, gddr_telemetry_table_t *gddr_telemetry)
Definition gddr.c:102
int32_t set_mrisc_power_setting(bool on)
Sets the MRISC power setting for all active MRISCs.
Definition gddr.c:526
__INT32_TYPE__ int32_t
__UINT8_TYPE__ uint8_t
Definition gddr_telemetry_table.h:21