TT Zephyr Platforms 19.5.0-rc1
Tenstorrent Firmware
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pll.c File Reference
#include "pll.h"
#include "reg.h"
#include "timer.h"
#include <stdbool.h>
#include <tenstorrent/post_code.h>
#include <tenstorrent/sys_init_defines.h>
#include <zephyr/init.h>
#include <zephyr/sys/util.h>

Data Structures

struct  PLL_CNTL_PLL_CNTL_0_reg_t
union  PLL_CNTL_PLL_CNTL_0_reg_u
struct  PLL_CNTL_PLL_CNTL_1_reg_t
union  PLL_CNTL_PLL_CNTL_1_reg_u
struct  PLL_CNTL_PLL_CNTL_2_reg_t
union  PLL_CNTL_PLL_CNTL_2_reg_u
struct  PLL_CNTL_PLL_CNTL_3_reg_t
union  PLL_CNTL_PLL_CNTL_3_reg_u
struct  PLL_CNTL_PLL_CNTL_4_reg_t
union  PLL_CNTL_PLL_CNTL_4_reg_u
struct  PLL_CNTL_PLL_CNTL_5_reg_t
union  PLL_CNTL_PLL_CNTL_5_reg_u
struct  PLL_CNTL_USE_POSTDIV_reg_t
union  PLL_CNTL_USE_POSTDIV_reg_u
struct  PLL_CNTL_WRAPPER_PLL_LOCK_reg_t
union  PLL_CNTL_WRAPPER_PLL_LOCK_reg_u
struct  PLLSettings

Macros

#define VCO_MIN_FREQ   1600
#define VCO_MAX_FREQ   5000
#define CLK_COUNTER_REFCLK_PERIOD   1000
#define PLL_0_CNTL_PLL_CNTL_0_REG_ADDR   0x80020100
#define PLL_0_CNTL_PLL_CNTL_1_REG_ADDR   0x80020104
#define PLL_0_CNTL_PLL_CNTL_2_REG_ADDR   0x80020108
#define PLL_0_CNTL_PLL_CNTL_3_REG_ADDR   0x8002010C
#define PLL_0_CNTL_PLL_CNTL_4_REG_ADDR   0x80020110
#define PLL_0_CNTL_PLL_CNTL_5_REG_ADDR   0x80020114
#define PLL_0_CNTL_PLL_CNTL_6_REG_ADDR   0x80020118
#define PLL_0_CNTL_USE_POSTDIV_REG_ADDR   0x8002011C
#define PLL_CNTL_WRAPPER_PLL_LOCK_REG_ADDR   0x80020040
#define PLL_CNTL_WRAPPER_REFCLK_PERIOD_REG_ADDR   0x8002002C
#define PLL_0_CNTL_CLK_COUNTER_EN_REG_ADDR   0x80020130
#define PLL_CNTL_PLL_CNTL_0_REG_DEFAULT   (0x00000000)
#define PLL_CNTL_PLL_CNTL_1_REG_DEFAULT   (0x00000000)
#define PLL_CNTL_PLL_CNTL_2_REG_DEFAULT   (0x00000000)
#define PLL_CNTL_PLL_CNTL_3_REG_DEFAULT   (0x00000000)
#define PLL_CNTL_PLL_CNTL_4_REG_DEFAULT   (0x00000000)
#define PLL_CNTL_PLL_CNTL_5_REG_DEFAULT   (0x00000000)
#define PLL_CNTL_USE_POSTDIV_REG_DEFAULT   (0x00000000)
#define PLL_CNTL_WRAPPER_PLL_LOCK_REG_DEFAULT   (0x00000000)
#define PLL_CNTL_REG_OFFSET   0x100
#define GET_PLL_CNTL_ADDR(ID, REG_NAME)

Enumerations

enum  PLLNum {
  PLL0 = 0 ,
  PLL1 = 1 ,
  PLL2 = 2 ,
  PLL3 = 3 ,
  PLL4 = 4 ,
  PLL_COUNT = 5
}
enum  PLLStatus {
  PLLOk = 0 ,
  PLLTimeout = 1
}

Functions

static void ConfigPLLVco (PLLNum pll_num, const PLLSettings *pll_settings)
static void ConfigExtPostDivs (PLLNum pll_num, const PLLSettings *pll_settings)
static void WaitPLLLock (PLLNum pll_num)
void PLLAllBypass (void)
void PLLUpdate (PLLNum pll, const PLLSettings *pll_settings)
static void enable_clk_counters (void)
int PLLInit (void)
 SYS_INIT_APP (PLLInit)
uint32_t GetExtPostdiv (uint8_t postdiv_index, PLL_CNTL_PLL_CNTL_5_reg_u pll_cntl_5, PLL_CNTL_USE_POSTDIV_reg_u use_postdiv)
uint32_t CalculateFreqFromPllRegs (PLL_CNTL_PLL_CNTL_1_reg_u pll_cntl_1, PLL_CNTL_PLL_CNTL_5_reg_u pll_cntl_5, PLL_CNTL_USE_POSTDIV_reg_u use_postdiv, uint8_t postdiv_index)
uint32_t CalculateFbdiv (uint32_t target_freq_mhz, PLL_CNTL_PLL_CNTL_1_reg_u pll_cntl_1, PLL_CNTL_PLL_CNTL_5_reg_u pll_cntl_5, PLL_CNTL_USE_POSTDIV_reg_u use_postdiv, uint8_t postdiv_index)
uint32_t GetVcoFreq (PLL_CNTL_PLL_CNTL_1_reg_u pll_cntl_1)
uint32_t GetFreqFromPll (PLLNum pll_num, uint8_t postdiv_index)
uint32_t GetAICLK (void)
uint32_t GetARCCLK (void)
uint32_t GetAXICLK (void)
uint32_t GetAPBCLK (void)
uint32_t GetL2CPUCLK (uint8_t l2cpu_num)
int SetGddrMemClk (uint32_t gddr_mem_clk_mhz)
void SetAICLK (uint32_t aiclk_in_mhz)
void DropAICLK (void)

Variables

static const PLLSettings kPLLInitialSettings [PLL_COUNT]

Macro Definition Documentation

◆ CLK_COUNTER_REFCLK_PERIOD

#define CLK_COUNTER_REFCLK_PERIOD   1000

◆ GET_PLL_CNTL_ADDR

#define GET_PLL_CNTL_ADDR ( ID,
REG_NAME )
Value:
(PLL_0_CNTL_##REG_NAME##_REG_ADDR + PLL_CNTL_REG_OFFSET * ID)
PLL_CNTL_REG_OFFSET
#define PLL_CNTL_REG_OFFSET
Definition pll.c:239

◆ PLL_0_CNTL_CLK_COUNTER_EN_REG_ADDR

#define PLL_0_CNTL_CLK_COUNTER_EN_REG_ADDR   0x80020130

◆ PLL_0_CNTL_PLL_CNTL_0_REG_ADDR

#define PLL_0_CNTL_PLL_CNTL_0_REG_ADDR   0x80020100

◆ PLL_0_CNTL_PLL_CNTL_1_REG_ADDR

#define PLL_0_CNTL_PLL_CNTL_1_REG_ADDR   0x80020104

◆ PLL_0_CNTL_PLL_CNTL_2_REG_ADDR

#define PLL_0_CNTL_PLL_CNTL_2_REG_ADDR   0x80020108

◆ PLL_0_CNTL_PLL_CNTL_3_REG_ADDR

#define PLL_0_CNTL_PLL_CNTL_3_REG_ADDR   0x8002010C

◆ PLL_0_CNTL_PLL_CNTL_4_REG_ADDR

#define PLL_0_CNTL_PLL_CNTL_4_REG_ADDR   0x80020110

◆ PLL_0_CNTL_PLL_CNTL_5_REG_ADDR

#define PLL_0_CNTL_PLL_CNTL_5_REG_ADDR   0x80020114

◆ PLL_0_CNTL_PLL_CNTL_6_REG_ADDR

#define PLL_0_CNTL_PLL_CNTL_6_REG_ADDR   0x80020118

◆ PLL_0_CNTL_USE_POSTDIV_REG_ADDR

#define PLL_0_CNTL_USE_POSTDIV_REG_ADDR   0x8002011C

◆ PLL_CNTL_PLL_CNTL_0_REG_DEFAULT

#define PLL_CNTL_PLL_CNTL_0_REG_DEFAULT   (0x00000000)

◆ PLL_CNTL_PLL_CNTL_1_REG_DEFAULT

#define PLL_CNTL_PLL_CNTL_1_REG_DEFAULT   (0x00000000)

◆ PLL_CNTL_PLL_CNTL_2_REG_DEFAULT

#define PLL_CNTL_PLL_CNTL_2_REG_DEFAULT   (0x00000000)

◆ PLL_CNTL_PLL_CNTL_3_REG_DEFAULT

#define PLL_CNTL_PLL_CNTL_3_REG_DEFAULT   (0x00000000)

◆ PLL_CNTL_PLL_CNTL_4_REG_DEFAULT

#define PLL_CNTL_PLL_CNTL_4_REG_DEFAULT   (0x00000000)

◆ PLL_CNTL_PLL_CNTL_5_REG_DEFAULT

#define PLL_CNTL_PLL_CNTL_5_REG_DEFAULT   (0x00000000)

◆ PLL_CNTL_REG_OFFSET

#define PLL_CNTL_REG_OFFSET   0x100

◆ PLL_CNTL_USE_POSTDIV_REG_DEFAULT

#define PLL_CNTL_USE_POSTDIV_REG_DEFAULT   (0x00000000)

◆ PLL_CNTL_WRAPPER_PLL_LOCK_REG_ADDR

#define PLL_CNTL_WRAPPER_PLL_LOCK_REG_ADDR   0x80020040

◆ PLL_CNTL_WRAPPER_PLL_LOCK_REG_DEFAULT

#define PLL_CNTL_WRAPPER_PLL_LOCK_REG_DEFAULT   (0x00000000)

◆ PLL_CNTL_WRAPPER_REFCLK_PERIOD_REG_ADDR

#define PLL_CNTL_WRAPPER_REFCLK_PERIOD_REG_ADDR   0x8002002C

◆ VCO_MAX_FREQ

#define VCO_MAX_FREQ   5000

◆ VCO_MIN_FREQ

#define VCO_MIN_FREQ   1600

Enumeration Type Documentation

◆ PLLNum

enum PLLNum
Enumerator
PLL0 0 
PLL1 1 
PLL2 2 
PLL3 3 
PLL4 4 
PLL_COUNT 5 

◆ PLLStatus

enum PLLStatus
Enumerator
PLLOk 0 
PLLTimeout 1 

Function Documentation

◆ CalculateFbdiv()

uint32_t CalculateFbdiv ( uint32_t target_freq_mhz,
PLL_CNTL_PLL_CNTL_1_reg_u pll_cntl_1,
PLL_CNTL_PLL_CNTL_5_reg_u pll_cntl_5,
PLL_CNTL_USE_POSTDIV_reg_u use_postdiv,
uint8_t postdiv_index )

◆ CalculateFreqFromPllRegs()

uint32_t CalculateFreqFromPllRegs ( PLL_CNTL_PLL_CNTL_1_reg_u pll_cntl_1,
PLL_CNTL_PLL_CNTL_5_reg_u pll_cntl_5,
PLL_CNTL_USE_POSTDIV_reg_u use_postdiv,
uint8_t postdiv_index )

◆ ConfigExtPostDivs()

void ConfigExtPostDivs ( PLLNum pll_num,
const PLLSettings * pll_settings )
static

◆ ConfigPLLVco()

void ConfigPLLVco ( PLLNum pll_num,
const PLLSettings * pll_settings )
static

◆ DropAICLK()

void DropAICLK ( void )

◆ enable_clk_counters()

void enable_clk_counters ( void )
static

◆ GetAICLK()

uint32_t GetAICLK ( void )

◆ GetAPBCLK()

uint32_t GetAPBCLK ( void )

◆ GetARCCLK()

uint32_t GetARCCLK ( void )

◆ GetAXICLK()

uint32_t GetAXICLK ( void )

◆ GetExtPostdiv()

uint32_t GetExtPostdiv ( uint8_t postdiv_index,
PLL_CNTL_PLL_CNTL_5_reg_u pll_cntl_5,
PLL_CNTL_USE_POSTDIV_reg_u use_postdiv )

◆ GetFreqFromPll()

uint32_t GetFreqFromPll ( PLLNum pll_num,
uint8_t postdiv_index )

◆ GetL2CPUCLK()

uint32_t GetL2CPUCLK ( uint8_t l2cpu_num)

◆ GetVcoFreq()

uint32_t GetVcoFreq ( PLL_CNTL_PLL_CNTL_1_reg_u pll_cntl_1)

◆ PLLAllBypass()

void PLLAllBypass ( void )

◆ PLLInit()

int PLLInit ( void )

◆ PLLUpdate()

void PLLUpdate ( PLLNum pll,
const PLLSettings * pll_settings )

◆ SetAICLK()

void SetAICLK ( uint32_t aiclk_in_mhz)

◆ SetGddrMemClk()

int SetGddrMemClk ( uint32_t gddr_mem_clk_mhz)

Attempt to set the requested GDDRMEMCLK frequency

This function tries to find a valid set of PLL settings to hit the requested GDDRMEMCLK frequency. It then updates the PLL if valid settings are found.

Returns
0 on success, -1 on failure

◆ SYS_INIT_APP()

SYS_INIT_APP ( PLLInit )

◆ WaitPLLLock()

void WaitPLLLock ( PLLNum pll_num)
static

Variable Documentation

◆ kPLLInitialSettings

const PLLSettings kPLLInitialSettings[PLL_COUNT]
static