TT Zephyr Platforms 18.11.99
Tenstorrent Firmware
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regulator_config.c File Reference
#include <stdint.h>
#include <zephyr/sys/util.h>
#include "regulator.h"
#include "regulator_config.h"

Macros

#define REGULATOR_DATA(regulator, cmd)

Functions

 BUILD_ASSERT (sizeof(p1x0_vcore_b0_data)==sizeof(p1x0_vcore_b0_mask))
 BUILD_ASSERT (sizeof(p1x0_vcore_cb_data)==sizeof(p1x0_vcore_cb_mask))
 BUILD_ASSERT (sizeof(p1x0_vcore_d3_data)==sizeof(p1x0_vcore_d3_mask))
 BUILD_ASSERT (sizeof(p1x0_vcore_ca_data)==sizeof(p1x0_vcore_ca_mask))
 BUILD_ASSERT (sizeof(p1x0_vcore_38_data)==sizeof(p1x0_vcore_38_mask))
 BUILD_ASSERT (sizeof(p1x0_vcore_39_data)==sizeof(p1x0_vcore_39_mask))
 BUILD_ASSERT (sizeof(p1x0_vcore_e7_data)==sizeof(p1x0_vcore_e7_mask))
 BUILD_ASSERT (sizeof(p1x0_vcorem_b0_data)==sizeof(p1x0_vcorem_b0_mask))
 BUILD_ASSERT (sizeof(p1x0_vcorem_38_data)==sizeof(p1x0_vcorem_38_mask))
 BUILD_ASSERT (sizeof(p1x0_vcorem_39_data)==sizeof(p1x0_vcorem_39_mask))
 BUILD_ASSERT (sizeof(p1x0_vcorem_e7_data)==sizeof(p1x0_vcorem_e7_mask))
 BUILD_ASSERT (sizeof(p300_vcore_b0_data)==sizeof(p300_vcore_b0_mask))
 BUILD_ASSERT (sizeof(p300_vcore_cb_data)==sizeof(p300_vcore_cb_mask))
 BUILD_ASSERT (sizeof(p300_vcore_38_data)==sizeof(p300_vcore_38_mask))
 BUILD_ASSERT (sizeof(p300_vcore_39_data)==sizeof(p300_vcore_39_mask))
 BUILD_ASSERT (sizeof(p300_vcore_e7_data)==sizeof(p300_vcore_e7_mask))
 BUILD_ASSERT (sizeof(p300_vcorem_b0_data)==sizeof(p300_vcorem_b0_mask))
 BUILD_ASSERT (sizeof(p300_vcorem_38_data)==sizeof(p300_vcorem_38_mask))
 BUILD_ASSERT (sizeof(p300_vcorem_39_data)==sizeof(p300_vcorem_39_mask))
 BUILD_ASSERT (sizeof(p300_vcorem_e7_data)==sizeof(p300_vcorem_e7_mask))
 BUILD_ASSERT (sizeof(ubb_vcore_b0_data)==sizeof(ubb_vcore_b0_mask))
 BUILD_ASSERT (sizeof(ubb_vcore_cb_data)==sizeof(ubb_vcore_cb_mask))
 BUILD_ASSERT (sizeof(ubb_vcore_d3_data)==sizeof(ubb_vcore_d3_mask))
 BUILD_ASSERT (sizeof(ubb_vcore_ca_data)==sizeof(ubb_vcore_ca_mask))
 BUILD_ASSERT (sizeof(ubb_vcore_38_data)==sizeof(ubb_vcore_38_mask))
 BUILD_ASSERT (sizeof(ubb_vcore_39_data)==sizeof(ubb_vcore_39_mask))
 BUILD_ASSERT (sizeof(ubb_vcore_e7_data)==sizeof(ubb_vcore_e7_mask))
 BUILD_ASSERT (sizeof(ubb_vcorem_b0_data)==sizeof(ubb_vcorem_b0_mask))
 BUILD_ASSERT (sizeof(ubb_vcorem_38_data)==sizeof(ubb_vcorem_38_mask))
 BUILD_ASSERT (sizeof(ubb_vcorem_39_data)==sizeof(ubb_vcorem_39_mask))
 BUILD_ASSERT (sizeof(ubb_vcorem_e7_data)==sizeof(ubb_vcorem_e7_mask))
 BUILD_ASSERT (sizeof(ubb_gddrio_29_data)==sizeof(ubb_gddrio_29_mask))
 BUILD_ASSERT (sizeof(ubb_gddrio_21_data)==sizeof(ubb_gddrio_21_mask))
 BUILD_ASSERT (sizeof(serdes_vr_d2_data)==sizeof(serdes_vr_d2_mask))

Variables

static const uint8_t p1x0_vcore_b0_data []
static const uint8_t p1x0_vcore_b0_mask []
static const uint8_t p1x0_vcore_cb_data [] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
static const uint8_t p1x0_vcore_cb_mask [] = {0x00, 0x07, 0x00, 0x00, 0x00, 0x00}
static const uint8_t p1x0_vcore_d3_data [] = {0x00}
static const uint8_t p1x0_vcore_d3_mask [] = {0x80}
static const uint8_t p1x0_vcore_ca_data [] = {0x00, 0x78, 0x00, 0x00, 0x00}
static const uint8_t p1x0_vcore_ca_mask [] = {0x00, 0xff, 0x00, 0x00, 0x00}
static const uint8_t p1x0_vcore_38_data [] = {0x08, 0x00}
static const uint8_t p1x0_vcore_38_mask [] = {0xff, 0x07}
static const uint8_t p1x0_vcore_39_data [] = {0x0c, 0x00}
static const uint8_t p1x0_vcore_39_mask [] = {0xff, 0x07}
static const uint8_t p1x0_vcore_e7_data [] = {0x01}
static const uint8_t p1x0_vcore_e7_mask [] = {0x07}
static const RegulatorData p1x0_vcore_data []
static const uint8_t p1x0_vcorem_b0_data []
static const uint8_t p1x0_vcorem_b0_mask []
static const uint8_t p1x0_vcorem_38_data [] = {0x08, 0x00}
static const uint8_t p1x0_vcorem_38_mask [] = {0xff, 0x07}
static const uint8_t p1x0_vcorem_39_data [] = {0x0c, 0x00}
static const uint8_t p1x0_vcorem_39_mask [] = {0xff, 0x07}
static const uint8_t p1x0_vcorem_e7_data [] = {0x04}
static const uint8_t p1x0_vcorem_e7_mask [] = {0x07}
static const RegulatorData p1x0_vcorem_data []
static const uint8_t p300_vcore_b0_data []
static const uint8_t p300_vcore_b0_mask []
static const uint8_t p300_vcore_cb_data [] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
static const uint8_t p300_vcore_cb_mask [] = {0x00, 0x07, 0x00, 0x00, 0x00, 0x00}
static const uint8_t p300_vcore_38_data [] = {0x02, 0x00}
static const uint8_t p300_vcore_38_mask [] = {0xff, 0x07}
static const uint8_t p300_vcore_39_data [] = {0x02, 0x00}
static const uint8_t p300_vcore_39_mask [] = {0xff, 0x07}
static const uint8_t p300_vcore_e7_data [] = {0x01}
static const uint8_t p300_vcore_e7_mask [] = {0x07}
static const RegulatorData p300_vcore_data []
static const uint8_t p300_vcorem_b0_data []
static const uint8_t p300_vcorem_b0_mask []
static const uint8_t p300_vcorem_38_data [] = {0x08, 0x00}
static const uint8_t p300_vcorem_38_mask [] = {0xff, 0x07}
static const uint8_t p300_vcorem_39_data [] = {0x0c, 0x00}
static const uint8_t p300_vcorem_39_mask [] = {0xff, 0x07}
static const uint8_t p300_vcorem_e7_data [] = {0x04}
static const uint8_t p300_vcorem_e7_mask [] = {0x07}
static const RegulatorData p300_vcorem_data []
static const uint8_t ubb_vcore_b0_data []
static const uint8_t ubb_vcore_b0_mask []
static const uint8_t ubb_vcore_cb_data [] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
static const uint8_t ubb_vcore_cb_mask [] = {0x00, 0x07, 0x00, 0x00, 0x00, 0x00}
static const uint8_t ubb_vcore_d3_data [] = {0x00}
static const uint8_t ubb_vcore_d3_mask [] = {0x80}
static const uint8_t ubb_vcore_ca_data [] = {0x00, 0x78, 0x00, 0x00, 0x00}
static const uint8_t ubb_vcore_ca_mask [] = {0x00, 0xff, 0x00, 0x00, 0x00}
static const uint8_t ubb_vcore_38_data [] = {0x02, 0x00}
static const uint8_t ubb_vcore_38_mask [] = {0xff, 0x07}
static const uint8_t ubb_vcore_39_data [] = {0x02, 0x00}
static const uint8_t ubb_vcore_39_mask [] = {0xff, 0x07}
static const uint8_t ubb_vcore_e7_data [] = {0x01}
static const uint8_t ubb_vcore_e7_mask [] = {0x07}
static const RegulatorData ubb_vcore_data []
static const uint8_t ubb_vcorem_b0_data []
static const uint8_t ubb_vcorem_b0_mask []
static const uint8_t ubb_vcorem_38_data [] = {0x02, 0x00}
static const uint8_t ubb_vcorem_38_mask [] = {0xff, 0x07}
static const uint8_t ubb_vcorem_39_data [] = {0x02, 0x00}
static const uint8_t ubb_vcorem_39_mask [] = {0xff, 0x07}
static const uint8_t ubb_vcorem_e7_data [] = {0x04}
static const uint8_t ubb_vcorem_e7_mask [] = {0x07}
static const RegulatorData ubb_vcorem_data []
static const uint8_t ubb_gddrio_29_data [] = {0xbc, 0x01}
static const uint8_t ubb_gddrio_29_mask [] = {0xff, 0xff}
static const uint8_t ubb_gddrio_21_data [] = {0xa3, 0x02}
static const uint8_t ubb_gddrio_21_mask [] = {0xff, 0xff}
static const RegulatorData ubb_gddrio_data []
static const uint8_t serdes_vr_d2_data [] = {0x07}
static const uint8_t serdes_vr_d2_mask [] = {0xff}
static const RegulatorData serdes_vr_data []
static const RegulatorConfig p150_config []
const BoardRegulatorsConfig p150_regulators_config
static const RegulatorConfig p300_left_config []
const BoardRegulatorsConfig p300_left_regulators_config
static const RegulatorConfig p300_right_config []
const BoardRegulatorsConfig p300_right_regulators_config
static const RegulatorConfig ubb_config []
const BoardRegulatorsConfig ubb_regulators_config

Macro Definition Documentation

◆ REGULATOR_DATA

#define REGULATOR_DATA ( regulator,
cmd )
Value:
{0x##cmd, regulator##_##cmd##_data, regulator##_##cmd##_mask, \
sizeof(regulator##_##cmd##_data)}
cmd
static void cmd(uint32_t command)

Function Documentation

◆ BUILD_ASSERT() [1/34]

BUILD_ASSERT ( sizeof(p1x0_vcore_38_data) = =sizeof(p1x0_vcore_38_mask))

◆ BUILD_ASSERT() [2/34]

BUILD_ASSERT ( sizeof(p1x0_vcore_39_data) = =sizeof(p1x0_vcore_39_mask))

◆ BUILD_ASSERT() [3/34]

BUILD_ASSERT ( sizeof(p1x0_vcore_b0_data) = =sizeof(p1x0_vcore_b0_mask))

◆ BUILD_ASSERT() [4/34]

BUILD_ASSERT ( sizeof(p1x0_vcore_ca_data) = =sizeof(p1x0_vcore_ca_mask))

◆ BUILD_ASSERT() [5/34]

BUILD_ASSERT ( sizeof(p1x0_vcore_cb_data) = =sizeof(p1x0_vcore_cb_mask))

◆ BUILD_ASSERT() [6/34]

BUILD_ASSERT ( sizeof(p1x0_vcore_d3_data) = =sizeof(p1x0_vcore_d3_mask))

◆ BUILD_ASSERT() [7/34]

BUILD_ASSERT ( sizeof(p1x0_vcore_e7_data) = =sizeof(p1x0_vcore_e7_mask))

◆ BUILD_ASSERT() [8/34]

BUILD_ASSERT ( sizeof(p1x0_vcorem_38_data) = =sizeof(p1x0_vcorem_38_mask))

◆ BUILD_ASSERT() [9/34]

BUILD_ASSERT ( sizeof(p1x0_vcorem_39_data) = =sizeof(p1x0_vcorem_39_mask))

◆ BUILD_ASSERT() [10/34]

BUILD_ASSERT ( sizeof(p1x0_vcorem_b0_data) = =sizeof(p1x0_vcorem_b0_mask))

◆ BUILD_ASSERT() [11/34]

BUILD_ASSERT ( sizeof(p1x0_vcorem_e7_data) = =sizeof(p1x0_vcorem_e7_mask))

◆ BUILD_ASSERT() [12/34]

BUILD_ASSERT ( sizeof(p300_vcore_38_data) = =sizeof(p300_vcore_38_mask))

◆ BUILD_ASSERT() [13/34]

BUILD_ASSERT ( sizeof(p300_vcore_39_data) = =sizeof(p300_vcore_39_mask))

◆ BUILD_ASSERT() [14/34]

BUILD_ASSERT ( sizeof(p300_vcore_b0_data) = =sizeof(p300_vcore_b0_mask))

◆ BUILD_ASSERT() [15/34]

BUILD_ASSERT ( sizeof(p300_vcore_cb_data) = =sizeof(p300_vcore_cb_mask))

◆ BUILD_ASSERT() [16/34]

BUILD_ASSERT ( sizeof(p300_vcore_e7_data) = =sizeof(p300_vcore_e7_mask))

◆ BUILD_ASSERT() [17/34]

BUILD_ASSERT ( sizeof(p300_vcorem_38_data) = =sizeof(p300_vcorem_38_mask))

◆ BUILD_ASSERT() [18/34]

BUILD_ASSERT ( sizeof(p300_vcorem_39_data) = =sizeof(p300_vcorem_39_mask))

◆ BUILD_ASSERT() [19/34]

BUILD_ASSERT ( sizeof(p300_vcorem_b0_data) = =sizeof(p300_vcorem_b0_mask))

◆ BUILD_ASSERT() [20/34]

BUILD_ASSERT ( sizeof(p300_vcorem_e7_data) = =sizeof(p300_vcorem_e7_mask))

◆ BUILD_ASSERT() [21/34]

BUILD_ASSERT ( sizeof(serdes_vr_d2_data) = =sizeof(serdes_vr_d2_mask))

◆ BUILD_ASSERT() [22/34]

BUILD_ASSERT ( sizeof(ubb_gddrio_21_data) = =sizeof(ubb_gddrio_21_mask))

◆ BUILD_ASSERT() [23/34]

BUILD_ASSERT ( sizeof(ubb_gddrio_29_data) = =sizeof(ubb_gddrio_29_mask))

◆ BUILD_ASSERT() [24/34]

BUILD_ASSERT ( sizeof(ubb_vcore_38_data) = =sizeof(ubb_vcore_38_mask))

◆ BUILD_ASSERT() [25/34]

BUILD_ASSERT ( sizeof(ubb_vcore_39_data) = =sizeof(ubb_vcore_39_mask))

◆ BUILD_ASSERT() [26/34]

BUILD_ASSERT ( sizeof(ubb_vcore_b0_data) = =sizeof(ubb_vcore_b0_mask))

◆ BUILD_ASSERT() [27/34]

BUILD_ASSERT ( sizeof(ubb_vcore_ca_data) = =sizeof(ubb_vcore_ca_mask))

◆ BUILD_ASSERT() [28/34]

BUILD_ASSERT ( sizeof(ubb_vcore_cb_data) = =sizeof(ubb_vcore_cb_mask))

◆ BUILD_ASSERT() [29/34]

BUILD_ASSERT ( sizeof(ubb_vcore_d3_data) = =sizeof(ubb_vcore_d3_mask))

◆ BUILD_ASSERT() [30/34]

BUILD_ASSERT ( sizeof(ubb_vcore_e7_data) = =sizeof(ubb_vcore_e7_mask))

◆ BUILD_ASSERT() [31/34]

BUILD_ASSERT ( sizeof(ubb_vcorem_38_data) = =sizeof(ubb_vcorem_38_mask))

◆ BUILD_ASSERT() [32/34]

BUILD_ASSERT ( sizeof(ubb_vcorem_39_data) = =sizeof(ubb_vcorem_39_mask))

◆ BUILD_ASSERT() [33/34]

BUILD_ASSERT ( sizeof(ubb_vcorem_b0_data) = =sizeof(ubb_vcorem_b0_mask))

◆ BUILD_ASSERT() [34/34]

BUILD_ASSERT ( sizeof(ubb_vcorem_e7_data) = =sizeof(ubb_vcorem_e7_mask))

Variable Documentation

◆ p150_config

const RegulatorConfig p150_config[]
static
Initial value:
= {
{
.address = 0x64 ,
.regulator_data = p1x0_vcore_data,
.count = ARRAY_SIZE(p1x0_vcore_data),
},
{
.address = 0x65 ,
.regulator_data = p1x0_vcorem_data,
.count = ARRAY_SIZE(p1x0_vcorem_data),
},
{
.address = 0x30 ,
.regulator_data = serdes_vr_data,
.count = ARRAY_SIZE(serdes_vr_data),
},
{
.address = 0x31 ,
.regulator_data = serdes_vr_data,
.count = ARRAY_SIZE(serdes_vr_data),
},
{
.address = 0x32 ,
.regulator_data = serdes_vr_data,
.count = ARRAY_SIZE(serdes_vr_data),
},
}
ARRAY_SIZE
#define ARRAY_SIZE(array)
serdes_vr_data
static const RegulatorData serdes_vr_data[]
Definition regulator_config.c:269
p1x0_vcorem_data
static const RegulatorData p1x0_vcorem_data[]
Definition regulator_config.c:86
p1x0_vcore_data
static const RegulatorData p1x0_vcore_data[]
Definition regulator_config.c:56

◆ p150_regulators_config

const BoardRegulatorsConfig p150_regulators_config
Initial value:
= {
.regulator_config = p150_config,
.count = ARRAY_SIZE(p150_config),
}
p150_config
static const RegulatorConfig p150_config[]
Definition regulator_config.c:275

◆ p1x0_vcore_38_data

const uint8_t p1x0_vcore_38_data[] = {0x08, 0x00}
static

◆ p1x0_vcore_38_mask

const uint8_t p1x0_vcore_38_mask[] = {0xff, 0x07}
static

◆ p1x0_vcore_39_data

const uint8_t p1x0_vcore_39_data[] = {0x0c, 0x00}
static

◆ p1x0_vcore_39_mask

const uint8_t p1x0_vcore_39_mask[] = {0xff, 0x07}
static

◆ p1x0_vcore_b0_data

const uint8_t p1x0_vcore_b0_data[]
static
Initial value:
= {0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00,
0x11, 0x00, 0x00, 0x00, 0x00, 0x41, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00}

◆ p1x0_vcore_b0_mask

const uint8_t p1x0_vcore_b0_mask[]
static
Initial value:
= {0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0x00, 0x00,
0x1f, 0x00, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00}

◆ p1x0_vcore_ca_data

const uint8_t p1x0_vcore_ca_data[] = {0x00, 0x78, 0x00, 0x00, 0x00}
static

◆ p1x0_vcore_ca_mask

const uint8_t p1x0_vcore_ca_mask[] = {0x00, 0xff, 0x00, 0x00, 0x00}
static

◆ p1x0_vcore_cb_data

const uint8_t p1x0_vcore_cb_data[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
static

◆ p1x0_vcore_cb_mask

const uint8_t p1x0_vcore_cb_mask[] = {0x00, 0x07, 0x00, 0x00, 0x00, 0x00}
static

◆ p1x0_vcore_d3_data

const uint8_t p1x0_vcore_d3_data[] = {0x00}
static

◆ p1x0_vcore_d3_mask

const uint8_t p1x0_vcore_d3_mask[] = {0x80}
static

◆ p1x0_vcore_data

const RegulatorData p1x0_vcore_data[]
static
Initial value:
= {
{0xb0, p1x0_vcore_b0_data, p1x0_vcore_b0_mask, sizeof(p1x0_vcore_b0_data)} , {0xcb, p1x0_vcore_cb_data, p1x0_vcore_cb_mask, sizeof(p1x0_vcore_cb_data)} ,
{0xd3, p1x0_vcore_d3_data, p1x0_vcore_d3_mask, sizeof(p1x0_vcore_d3_data)} , {0xca, p1x0_vcore_ca_data, p1x0_vcore_ca_mask, sizeof(p1x0_vcore_ca_data)} ,
{0x38, p1x0_vcore_38_data, p1x0_vcore_38_mask, sizeof(p1x0_vcore_38_data)} , {0x39, p1x0_vcore_39_data, p1x0_vcore_39_mask, sizeof(p1x0_vcore_39_data)} ,
{0xe7, p1x0_vcore_e7_data, p1x0_vcore_e7_mask, sizeof(p1x0_vcore_e7_data)} ,
}
p1x0_vcore_d3_mask
static const uint8_t p1x0_vcore_d3_mask[]
Definition regulator_config.c:32
p1x0_vcore_cb_mask
static const uint8_t p1x0_vcore_cb_mask[]
Definition regulator_config.c:27
p1x0_vcore_38_data
static const uint8_t p1x0_vcore_38_data[]
Definition regulator_config.c:41
p1x0_vcore_cb_data
static const uint8_t p1x0_vcore_cb_data[]
Definition regulator_config.c:26
p1x0_vcore_d3_data
static const uint8_t p1x0_vcore_d3_data[]
Definition regulator_config.c:31
p1x0_vcore_b0_data
static const uint8_t p1x0_vcore_b0_data[]
Definition regulator_config.c:17
p1x0_vcore_ca_data
static const uint8_t p1x0_vcore_ca_data[]
Definition regulator_config.c:36
p1x0_vcore_b0_mask
static const uint8_t p1x0_vcore_b0_mask[]
Definition regulator_config.c:20
p1x0_vcore_e7_data
static const uint8_t p1x0_vcore_e7_data[]
Definition regulator_config.c:51
p1x0_vcore_ca_mask
static const uint8_t p1x0_vcore_ca_mask[]
Definition regulator_config.c:37
p1x0_vcore_39_data
static const uint8_t p1x0_vcore_39_data[]
Definition regulator_config.c:46
p1x0_vcore_39_mask
static const uint8_t p1x0_vcore_39_mask[]
Definition regulator_config.c:47
p1x0_vcore_38_mask
static const uint8_t p1x0_vcore_38_mask[]
Definition regulator_config.c:42
p1x0_vcore_e7_mask
static const uint8_t p1x0_vcore_e7_mask[]
Definition regulator_config.c:52

◆ p1x0_vcore_e7_data

const uint8_t p1x0_vcore_e7_data[] = {0x01}
static

◆ p1x0_vcore_e7_mask

const uint8_t p1x0_vcore_e7_mask[] = {0x07}
static

◆ p1x0_vcorem_38_data

const uint8_t p1x0_vcorem_38_data[] = {0x08, 0x00}
static

◆ p1x0_vcorem_38_mask

const uint8_t p1x0_vcorem_38_mask[] = {0xff, 0x07}
static

◆ p1x0_vcorem_39_data

const uint8_t p1x0_vcorem_39_data[] = {0x0c, 0x00}
static

◆ p1x0_vcorem_39_mask

const uint8_t p1x0_vcorem_39_mask[] = {0xff, 0x07}
static

◆ p1x0_vcorem_b0_data

const uint8_t p1x0_vcorem_b0_data[]
static
Initial value:
= {0x00, 0x00, 0x2b, 0x00, 0x00, 0x07, 0x00, 0x00,
0x09, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00}

◆ p1x0_vcorem_b0_mask

const uint8_t p1x0_vcorem_b0_mask[]
static
Initial value:
= {0x00, 0x00, 0x3f, 0x00, 0x00, 0x1f, 0x00, 0x00,
0x1f, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00}

◆ p1x0_vcorem_data

const RegulatorData p1x0_vcorem_data[]
static
Initial value:
= {
{0xb0, p1x0_vcorem_b0_data, p1x0_vcorem_b0_mask, sizeof(p1x0_vcorem_b0_data)} ,
{0x38, p1x0_vcorem_38_data, p1x0_vcorem_38_mask, sizeof(p1x0_vcorem_38_data)} ,
{0x39, p1x0_vcorem_39_data, p1x0_vcorem_39_mask, sizeof(p1x0_vcorem_39_data)} ,
{0xe7, p1x0_vcorem_e7_data, p1x0_vcorem_e7_mask, sizeof(p1x0_vcorem_e7_data)} ,
}
p1x0_vcorem_e7_data
static const uint8_t p1x0_vcorem_e7_data[]
Definition regulator_config.c:81
p1x0_vcorem_b0_mask
static const uint8_t p1x0_vcorem_b0_mask[]
Definition regulator_config.c:66
p1x0_vcorem_e7_mask
static const uint8_t p1x0_vcorem_e7_mask[]
Definition regulator_config.c:82
p1x0_vcorem_b0_data
static const uint8_t p1x0_vcorem_b0_data[]
Definition regulator_config.c:64
p1x0_vcorem_38_mask
static const uint8_t p1x0_vcorem_38_mask[]
Definition regulator_config.c:72
p1x0_vcorem_39_mask
static const uint8_t p1x0_vcorem_39_mask[]
Definition regulator_config.c:77
p1x0_vcorem_39_data
static const uint8_t p1x0_vcorem_39_data[]
Definition regulator_config.c:76
p1x0_vcorem_38_data
static const uint8_t p1x0_vcorem_38_data[]
Definition regulator_config.c:71

◆ p1x0_vcorem_e7_data

const uint8_t p1x0_vcorem_e7_data[] = {0x04}
static

◆ p1x0_vcorem_e7_mask

const uint8_t p1x0_vcorem_e7_mask[] = {0x07}
static

◆ p300_left_config

const RegulatorConfig p300_left_config[]
static
Initial value:
= {
{
.address = 0x64 ,
.regulator_data = p300_vcore_data,
.count = ARRAY_SIZE(p300_vcore_data),
},
{
.address = 0x65 ,
.regulator_data = p300_vcorem_data,
.count = ARRAY_SIZE(p300_vcorem_data),
},
{
.address = 0x30 ,
.regulator_data = serdes_vr_data,
.count = ARRAY_SIZE(serdes_vr_data),
},
{
.address = 0x32 ,
.regulator_data = serdes_vr_data,
.count = ARRAY_SIZE(serdes_vr_data),
},
}
p300_vcorem_data
static const RegulatorData p300_vcorem_data[]
Definition regulator_config.c:156
p300_vcore_data
static const RegulatorData p300_vcore_data[]
Definition regulator_config.c:127

◆ p300_left_regulators_config

const BoardRegulatorsConfig p300_left_regulators_config
Initial value:
= {
.regulator_config = p300_left_config,
.count = ARRAY_SIZE(p300_left_config),
}
p300_left_config
static const RegulatorConfig p300_left_config[]
Definition regulator_config.c:308

◆ p300_right_config

const RegulatorConfig p300_right_config[]
static
Initial value:
= {
{
.address = 0x64 ,
.regulator_data = p300_vcore_data,
.count = ARRAY_SIZE(p300_vcore_data),
},
{
.address = 0x65 ,
.regulator_data = p300_vcorem_data,
.count = ARRAY_SIZE(p300_vcorem_data),
},
{
.address = 0x30 ,
.regulator_data = serdes_vr_data,
.count = ARRAY_SIZE(serdes_vr_data),
},
{
.address = 0x31 ,
.regulator_data = serdes_vr_data,
.count = ARRAY_SIZE(serdes_vr_data),
},
{
.address = 0x32 ,
.regulator_data = serdes_vr_data,
.count = ARRAY_SIZE(serdes_vr_data),
},
}

◆ p300_right_regulators_config

const BoardRegulatorsConfig p300_right_regulators_config
Initial value:
= {
.regulator_config = p300_right_config,
.count = ARRAY_SIZE(p300_right_config),
}
p300_right_config
static const RegulatorConfig p300_right_config[]
Definition regulator_config.c:337

◆ p300_vcore_38_data

const uint8_t p300_vcore_38_data[] = {0x02, 0x00}
static

◆ p300_vcore_38_mask

const uint8_t p300_vcore_38_mask[] = {0xff, 0x07}
static

◆ p300_vcore_39_data

const uint8_t p300_vcore_39_data[] = {0x02, 0x00}
static

◆ p300_vcore_39_mask

const uint8_t p300_vcore_39_mask[] = {0xff, 0x07}
static

◆ p300_vcore_b0_data

const uint8_t p300_vcore_b0_data[]
static
Initial value:
= {0x00, 0x00, 0x3c, 0x00, 0x00, 0x03, 0x00, 0x00,
0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00}

◆ p300_vcore_b0_mask

const uint8_t p300_vcore_b0_mask[]
static
Initial value:
= {0x00, 0x00, 0x3f, 0x00, 0x00, 0x1f, 0x00, 0x00,
0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00}

◆ p300_vcore_cb_data

const uint8_t p300_vcore_cb_data[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
static

◆ p300_vcore_cb_mask

const uint8_t p300_vcore_cb_mask[] = {0x00, 0x07, 0x00, 0x00, 0x00, 0x00}
static

◆ p300_vcore_data

const RegulatorData p300_vcore_data[]
static
Initial value:
= {
{0xb0, p300_vcore_b0_data, p300_vcore_b0_mask, sizeof(p300_vcore_b0_data)} , {0xcb, p300_vcore_cb_data, p300_vcore_cb_mask, sizeof(p300_vcore_cb_data)} ,
{0x38, p300_vcore_38_data, p300_vcore_38_mask, sizeof(p300_vcore_38_data)} , {0x39, p300_vcore_39_data, p300_vcore_39_mask, sizeof(p300_vcore_39_data)} ,
{0xe7, p300_vcore_e7_data, p300_vcore_e7_mask, sizeof(p300_vcore_e7_data)} ,
}
p300_vcore_cb_data
static const uint8_t p300_vcore_cb_data[]
Definition regulator_config.c:107
p300_vcore_b0_data
static const uint8_t p300_vcore_b0_data[]
Definition regulator_config.c:98
p300_vcore_b0_mask
static const uint8_t p300_vcore_b0_mask[]
Definition regulator_config.c:101
p300_vcore_cb_mask
static const uint8_t p300_vcore_cb_mask[]
Definition regulator_config.c:108
p300_vcore_e7_mask
static const uint8_t p300_vcore_e7_mask[]
Definition regulator_config.c:123
p300_vcore_38_mask
static const uint8_t p300_vcore_38_mask[]
Definition regulator_config.c:113
p300_vcore_39_data
static const uint8_t p300_vcore_39_data[]
Definition regulator_config.c:117
p300_vcore_e7_data
static const uint8_t p300_vcore_e7_data[]
Definition regulator_config.c:122
p300_vcore_38_data
static const uint8_t p300_vcore_38_data[]
Definition regulator_config.c:112
p300_vcore_39_mask
static const uint8_t p300_vcore_39_mask[]
Definition regulator_config.c:118

◆ p300_vcore_e7_data

const uint8_t p300_vcore_e7_data[] = {0x01}
static

◆ p300_vcore_e7_mask

const uint8_t p300_vcore_e7_mask[] = {0x07}
static

◆ p300_vcorem_38_data

const uint8_t p300_vcorem_38_data[] = {0x08, 0x00}
static

◆ p300_vcorem_38_mask

const uint8_t p300_vcorem_38_mask[] = {0xff, 0x07}
static

◆ p300_vcorem_39_data

const uint8_t p300_vcorem_39_data[] = {0x0c, 0x00}
static

◆ p300_vcorem_39_mask

const uint8_t p300_vcorem_39_mask[] = {0xff, 0x07}
static

◆ p300_vcorem_b0_data

const uint8_t p300_vcorem_b0_data[]
static
Initial value:
= {0x00, 0x00, 0x2b, 0x00, 0x00, 0x07, 0x00, 0x00,
0x09, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00}

◆ p300_vcorem_b0_mask

const uint8_t p300_vcorem_b0_mask[]
static
Initial value:
= {0x00, 0x00, 0x3f, 0x00, 0x00, 0x1f, 0x00, 0x00,
0x1f, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00}

◆ p300_vcorem_data

const RegulatorData p300_vcorem_data[]
static
Initial value:
= {
{0xb0, p300_vcorem_b0_data, p300_vcorem_b0_mask, sizeof(p300_vcorem_b0_data)} ,
{0x38, p300_vcorem_38_data, p300_vcorem_38_mask, sizeof(p300_vcorem_38_data)} ,
{0x39, p300_vcorem_39_data, p300_vcorem_39_mask, sizeof(p300_vcorem_39_data)} ,
{0xe7, p300_vcorem_e7_data, p300_vcorem_e7_mask, sizeof(p300_vcorem_e7_data)} ,
}
p300_vcorem_b0_mask
static const uint8_t p300_vcorem_b0_mask[]
Definition regulator_config.c:136
p300_vcorem_39_data
static const uint8_t p300_vcorem_39_data[]
Definition regulator_config.c:146
p300_vcorem_e7_mask
static const uint8_t p300_vcorem_e7_mask[]
Definition regulator_config.c:152
p300_vcorem_38_data
static const uint8_t p300_vcorem_38_data[]
Definition regulator_config.c:141
p300_vcorem_39_mask
static const uint8_t p300_vcorem_39_mask[]
Definition regulator_config.c:147
p300_vcorem_b0_data
static const uint8_t p300_vcorem_b0_data[]
Definition regulator_config.c:134
p300_vcorem_38_mask
static const uint8_t p300_vcorem_38_mask[]
Definition regulator_config.c:142
p300_vcorem_e7_data
static const uint8_t p300_vcorem_e7_data[]
Definition regulator_config.c:151

◆ p300_vcorem_e7_data

const uint8_t p300_vcorem_e7_data[] = {0x04}
static

◆ p300_vcorem_e7_mask

const uint8_t p300_vcorem_e7_mask[] = {0x07}
static

◆ serdes_vr_d2_data

const uint8_t serdes_vr_d2_data[] = {0x07}
static

◆ serdes_vr_d2_mask

const uint8_t serdes_vr_d2_mask[] = {0xff}
static

◆ serdes_vr_data

const RegulatorData serdes_vr_data[]
static
Initial value:
= {
{0xd2, serdes_vr_d2_data, serdes_vr_d2_mask, sizeof(serdes_vr_d2_data)} ,
}
serdes_vr_d2_data
static const uint8_t serdes_vr_d2_data[]
Definition regulator_config.c:264
serdes_vr_d2_mask
static const uint8_t serdes_vr_d2_mask[]
Definition regulator_config.c:265

◆ ubb_config

const RegulatorConfig ubb_config[]
static
Initial value:
= {
{
.address = 0x64 ,
.regulator_data = ubb_vcore_data,
.count = ARRAY_SIZE(ubb_vcore_data),
},
{
.address = 0x65 ,
.regulator_data = ubb_vcorem_data,
.count = ARRAY_SIZE(ubb_vcorem_data),
},
{
.address = 0x36 ,
.regulator_data = ubb_gddrio_data,
.count = ARRAY_SIZE(ubb_gddrio_data),
},
{
.address = 0x37 ,
.regulator_data = ubb_gddrio_data,
.count = ARRAY_SIZE(ubb_gddrio_data),
},
}
ubb_vcorem_data
static const RegulatorData ubb_vcorem_data[]
Definition regulator_config.c:236
ubb_vcore_data
static const RegulatorData ubb_vcore_data[]
Definition regulator_config.c:207
ubb_gddrio_data
static const RegulatorData ubb_gddrio_data[]
Definition regulator_config.c:255

◆ ubb_gddrio_21_data

const uint8_t ubb_gddrio_21_data[] = {0xa3, 0x02}
static

◆ ubb_gddrio_21_mask

const uint8_t ubb_gddrio_21_mask[] = {0xff, 0xff}
static

◆ ubb_gddrio_29_data

const uint8_t ubb_gddrio_29_data[] = {0xbc, 0x01}
static

◆ ubb_gddrio_29_mask

const uint8_t ubb_gddrio_29_mask[] = {0xff, 0xff}
static

◆ ubb_gddrio_data

const RegulatorData ubb_gddrio_data[]
static
Initial value:
= {
{0x29, ubb_gddrio_29_data, ubb_gddrio_29_mask, sizeof(ubb_gddrio_29_data)} ,
{0x21, ubb_gddrio_21_data, ubb_gddrio_21_mask, sizeof(ubb_gddrio_21_data)} ,
}
ubb_gddrio_21_data
static const uint8_t ubb_gddrio_21_data[]
Definition regulator_config.c:250
ubb_gddrio_21_mask
static const uint8_t ubb_gddrio_21_mask[]
Definition regulator_config.c:251
ubb_gddrio_29_mask
static const uint8_t ubb_gddrio_29_mask[]
Definition regulator_config.c:245
ubb_gddrio_29_data
static const uint8_t ubb_gddrio_29_data[]
Definition regulator_config.c:244

◆ ubb_regulators_config

const BoardRegulatorsConfig ubb_regulators_config
Initial value:
= {
.regulator_config = ubb_config,
.count = ARRAY_SIZE(ubb_config),
}
ubb_config
static const RegulatorConfig ubb_config[]
Definition regulator_config.c:370

◆ ubb_vcore_38_data

const uint8_t ubb_vcore_38_data[] = {0x02, 0x00}
static

◆ ubb_vcore_38_mask

const uint8_t ubb_vcore_38_mask[] = {0xff, 0x07}
static

◆ ubb_vcore_39_data

const uint8_t ubb_vcore_39_data[] = {0x02, 0x00}
static

◆ ubb_vcore_39_mask

const uint8_t ubb_vcore_39_mask[] = {0xff, 0x07}
static

◆ ubb_vcore_b0_data

const uint8_t ubb_vcore_b0_data[]
static
Initial value:
= {0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x06, 0x00,
0x11, 0x00, 0x00, 0x00, 0x00, 0x41, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00}

◆ ubb_vcore_b0_mask

const uint8_t ubb_vcore_b0_mask[]
static
Initial value:
= {0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0x0f, 0x00,
0x1f, 0x00, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00}

◆ ubb_vcore_ca_data

const uint8_t ubb_vcore_ca_data[] = {0x00, 0x78, 0x00, 0x00, 0x00}
static

◆ ubb_vcore_ca_mask

const uint8_t ubb_vcore_ca_mask[] = {0x00, 0xff, 0x00, 0x00, 0x00}
static

◆ ubb_vcore_cb_data

const uint8_t ubb_vcore_cb_data[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
static

◆ ubb_vcore_cb_mask

const uint8_t ubb_vcore_cb_mask[] = {0x00, 0x07, 0x00, 0x00, 0x00, 0x00}
static

◆ ubb_vcore_d3_data

const uint8_t ubb_vcore_d3_data[] = {0x00}
static

◆ ubb_vcore_d3_mask

const uint8_t ubb_vcore_d3_mask[] = {0x80}
static

◆ ubb_vcore_data

const RegulatorData ubb_vcore_data[]
static
Initial value:
= {
{0xb0, ubb_vcore_b0_data, ubb_vcore_b0_mask, sizeof(ubb_vcore_b0_data)} , {0xcb, ubb_vcore_cb_data, ubb_vcore_cb_mask, sizeof(ubb_vcore_cb_data)} , {0xd3, ubb_vcore_d3_data, ubb_vcore_d3_mask, sizeof(ubb_vcore_d3_data)} ,
{0xca, ubb_vcore_ca_data, ubb_vcore_ca_mask, sizeof(ubb_vcore_ca_data)} , {0x38, ubb_vcore_38_data, ubb_vcore_38_mask, sizeof(ubb_vcore_38_data)} , {0x39, ubb_vcore_39_data, ubb_vcore_39_mask, sizeof(ubb_vcore_39_data)} ,
{0xe7, ubb_vcore_e7_data, ubb_vcore_e7_mask, sizeof(ubb_vcore_e7_data)} ,
}
ubb_vcore_d3_mask
static const uint8_t ubb_vcore_d3_mask[]
Definition regulator_config.c:183
ubb_vcore_38_mask
static const uint8_t ubb_vcore_38_mask[]
Definition regulator_config.c:193
ubb_vcore_39_data
static const uint8_t ubb_vcore_39_data[]
Definition regulator_config.c:197
ubb_vcore_e7_mask
static const uint8_t ubb_vcore_e7_mask[]
Definition regulator_config.c:203
ubb_vcore_b0_mask
static const uint8_t ubb_vcore_b0_mask[]
Definition regulator_config.c:171
ubb_vcore_ca_data
static const uint8_t ubb_vcore_ca_data[]
Definition regulator_config.c:187
ubb_vcore_cb_data
static const uint8_t ubb_vcore_cb_data[]
Definition regulator_config.c:177
ubb_vcore_e7_data
static const uint8_t ubb_vcore_e7_data[]
Definition regulator_config.c:202
ubb_vcore_b0_data
static const uint8_t ubb_vcore_b0_data[]
Definition regulator_config.c:168
ubb_vcore_cb_mask
static const uint8_t ubb_vcore_cb_mask[]
Definition regulator_config.c:178
ubb_vcore_39_mask
static const uint8_t ubb_vcore_39_mask[]
Definition regulator_config.c:198
ubb_vcore_d3_data
static const uint8_t ubb_vcore_d3_data[]
Definition regulator_config.c:182
ubb_vcore_ca_mask
static const uint8_t ubb_vcore_ca_mask[]
Definition regulator_config.c:188
ubb_vcore_38_data
static const uint8_t ubb_vcore_38_data[]
Definition regulator_config.c:192

◆ ubb_vcore_e7_data

const uint8_t ubb_vcore_e7_data[] = {0x01}
static

◆ ubb_vcore_e7_mask

const uint8_t ubb_vcore_e7_mask[] = {0x07}
static

◆ ubb_vcorem_38_data

const uint8_t ubb_vcorem_38_data[] = {0x02, 0x00}
static

◆ ubb_vcorem_38_mask

const uint8_t ubb_vcorem_38_mask[] = {0xff, 0x07}
static

◆ ubb_vcorem_39_data

const uint8_t ubb_vcorem_39_data[] = {0x02, 0x00}
static

◆ ubb_vcorem_39_mask

const uint8_t ubb_vcorem_39_mask[] = {0xff, 0x07}
static

◆ ubb_vcorem_b0_data

const uint8_t ubb_vcorem_b0_data[]
static
Initial value:
= {0x00, 0x00, 0x2b, 0x00, 0x00, 0x07, 0x00, 0x00,
0x09, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00}

◆ ubb_vcorem_b0_mask

const uint8_t ubb_vcorem_b0_mask[]
static
Initial value:
= {0x00, 0x00, 0x3f, 0x00, 0x00, 0x1f, 0x00, 0x00,
0x1f, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00}

◆ ubb_vcorem_data

const RegulatorData ubb_vcorem_data[]
static
Initial value:
= {
{0xb0, ubb_vcorem_b0_data, ubb_vcorem_b0_mask, sizeof(ubb_vcorem_b0_data)} ,
{0x38, ubb_vcorem_38_data, ubb_vcorem_38_mask, sizeof(ubb_vcorem_38_data)} ,
{0x39, ubb_vcorem_39_data, ubb_vcorem_39_mask, sizeof(ubb_vcorem_39_data)} ,
{0xe7, ubb_vcorem_e7_data, ubb_vcorem_e7_mask, sizeof(ubb_vcorem_e7_data)} ,
}
ubb_vcorem_39_data
static const uint8_t ubb_vcorem_39_data[]
Definition regulator_config.c:226
ubb_vcorem_b0_mask
static const uint8_t ubb_vcorem_b0_mask[]
Definition regulator_config.c:216
ubb_vcorem_e7_mask
static const uint8_t ubb_vcorem_e7_mask[]
Definition regulator_config.c:232
ubb_vcorem_b0_data
static const uint8_t ubb_vcorem_b0_data[]
Definition regulator_config.c:214
ubb_vcorem_39_mask
static const uint8_t ubb_vcorem_39_mask[]
Definition regulator_config.c:227
ubb_vcorem_38_mask
static const uint8_t ubb_vcorem_38_mask[]
Definition regulator_config.c:222
ubb_vcorem_e7_data
static const uint8_t ubb_vcorem_e7_data[]
Definition regulator_config.c:231
ubb_vcorem_38_data
static const uint8_t ubb_vcorem_38_data[]
Definition regulator_config.c:221

◆ ubb_vcorem_e7_data

const uint8_t ubb_vcorem_e7_data[] = {0x04}
static

◆ ubb_vcorem_e7_mask

const uint8_t ubb_vcorem_e7_mask[] = {0x07}
static