status_reg.h

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/*
 * Copyright (c) 2024 Tenstorrent AI ULC
 * SPDX-License-Identifier: Apache-2.0
 */
 
/* Scratch registers used for status and error reporting */
#ifndef STATUS_REG_H
#define STATUS_REG_H
 
#include <stdint.h>
 
#define RESET_UNIT_SCRATCH_RAM_BASE_ADDR 0x80030400
#define RESET_UNIT_SCRATCH_RAM_REG_ADDR(n)                                                         \
        (RESET_UNIT_SCRATCH_RAM_BASE_ADDR + sizeof(uint32_t) * (n))
 
#define RESET_UNIT_SCRATCH_BASE_ADDR   0x80030060
#define RESET_UNIT_SCRATCH_REG_ADDR(n) (RESET_UNIT_SCRATCH_BASE_ADDR + sizeof(uint32_t) * (n))
 
/* SCRATCH_[0-7] */
#define STATUS_POST_CODE_REG_ADDR RESET_UNIT_SCRATCH_REG_ADDR(0)
 
/* SCRATCH_RAM[0-63] */
#define STATUS_FW_VERSION_REG_ADDR           RESET_UNIT_SCRATCH_RAM_REG_ADDR(0)
/* SCRATCH_RAM_1 is reserved for the security handshake used by bootcode */
#define STATUS_BOOT_STATUS0_REG_ADDR         RESET_UNIT_SCRATCH_RAM_REG_ADDR(2)
#define STATUS_BOOT_STATUS1_REG_ADDR         RESET_UNIT_SCRATCH_RAM_REG_ADDR(3)
#define STATUS_ERROR_STATUS0_REG_ADDR        RESET_UNIT_SCRATCH_RAM_REG_ADDR(4)
#define STATUS_ERROR_STATUS1_REG_ADDR        RESET_UNIT_SCRATCH_RAM_REG_ADDR(5)
#define STATUS_INTERFACE_TABLE_BASE_REG_ADDR RESET_UNIT_SCRATCH_RAM_REG_ADDR(6)
/* SCRATCH_RAM_7 is reserved for possible future interface table uses */
#define STATUS_MSG_Q_STATUS_REG_ADDR         RESET_UNIT_SCRATCH_RAM_REG_ADDR(8)
#define STATUS_MSG_Q_ERR_FLAGS_REG_ADDR      RESET_UNIT_SCRATCH_RAM_REG_ADDR(9)
#define SPI_BUFFER_INFO_REG_ADDR             RESET_UNIT_SCRATCH_RAM_REG_ADDR(10)
#define STATUS_MSG_Q_INFO_REG_ADDR           RESET_UNIT_SCRATCH_RAM_REG_ADDR(11)
#define TELEMETRY_DATA_REG_ADDR              RESET_UNIT_SCRATCH_RAM_REG_ADDR(12)
#define TELEMETRY_TABLE_REG_ADDR             RESET_UNIT_SCRATCH_RAM_REG_ADDR(13)
#define PCIE_INIT_CPL_TIME_REG_ADDR          RESET_UNIT_SCRATCH_RAM_REG_ADDR(14)
#define CMFW_START_TIME_REG_ADDR             RESET_UNIT_SCRATCH_RAM_REG_ADDR(15)
#define ARC_START_TIME_REG_ADDR              RESET_UNIT_SCRATCH_RAM_REG_ADDR(16)
#define PERST_TO_DMFW_INIT_DONE_REG_ADDR     RESET_UNIT_SCRATCH_RAM_REG_ADDR(17)
#define PING_DMFW_DURATION_REG_ADDR          RESET_UNIT_SCRATCH_RAM_REG_ADDR(18)
#define I2C0_TARGET_DEBUG_STATE_REG_ADDR     RESET_UNIT_SCRATCH_RAM_REG_ADDR(19)
#define I2C0_TARGET_DEBUG_STATE_2_REG_ADDR   RESET_UNIT_SCRATCH_RAM_REG_ADDR(20)
#define ARC_HANG_PC                          RESET_UNIT_SCRATCH_RAM_REG_ADDR(21)
 
#define STATUS_FW_VUART_REG_ADDR(n)          RESET_UNIT_SCRATCH_RAM_REG_ADDR(40 + (n))
/* SCRATCH_RAM_40 - SCRATCH_RAM_41 reserved for virtual uarts */
#define STATUS_FW_SCRATCH_REG_ADDR           RESET_UNIT_SCRATCH_RAM_REG_ADDR(63)
 
typedef struct {
        uint32_t msg_queue_ready: 1;
        uint32_t hw_init_status: 2;
        uint32_t fw_id: 4;
        uint32_t spare: 25;
} STATUS_BOOT_STATUS0_reg_t;
 
typedef union {
        uint32_t val;
        STATUS_BOOT_STATUS0_reg_t f;
} STATUS_BOOT_STATUS0_reg_u;
 
typedef struct {
        uint32_t regulator_init_error: 1;
} STATUS_ERROR_STATUS0_reg_t;
 
typedef union {
        uint32_t val;
        STATUS_ERROR_STATUS0_reg_t f;
} STATUS_ERROR_STATUS0_reg_u;
 
#endif