RESET_UNIT_PCIE_MISC_CNTL3_reg_t Struct Reference

Data Fields
uint32_t	sd_mode_sel_0: 1
uint32_t	sd_mode_sel_1: 1
uint32_t	reserved_2: 1
uint32_t	mux_sel: 2
uint32_t	master_sel_0: 2
uint32_t	master_sel_1: 2
uint32_t	master_sel_2: 2
uint32_t	reserved_31_11: 21

Field Documentation

master_sel_0

uint32_t RESET_UNIT_PCIE_MISC_CNTL3_reg_t::master_sel_0

master_sel_1

uint32_t RESET_UNIT_PCIE_MISC_CNTL3_reg_t::master_sel_1

master_sel_2

uint32_t RESET_UNIT_PCIE_MISC_CNTL3_reg_t::master_sel_2

mux_sel

uint32_t RESET_UNIT_PCIE_MISC_CNTL3_reg_t::mux_sel

reserved_2

uint32_t RESET_UNIT_PCIE_MISC_CNTL3_reg_t::reserved_2

reserved_31_11

uint32_t RESET_UNIT_PCIE_MISC_CNTL3_reg_t::reserved_31_11

sd_mode_sel_0

uint32_t RESET_UNIT_PCIE_MISC_CNTL3_reg_t::sd_mode_sel_0

sd_mode_sel_1

uint32_t RESET_UNIT_PCIE_MISC_CNTL3_reg_t::sd_mode_sel_1

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The documentation for this struct was generated from the following file:

• /home/runner/work/tt-zephyr-platforms/tt-zephyr-platforms/tt-zephyr-platforms/lib/tenstorrent/bh_arc/eth.c