gddr.h

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/*
 * Copyright (c) 2024 Tenstorrent AI ULC
 * SPDX-License-Identifier: Apache-2.0
 */
 
#ifndef _GDDR_H_
#define _GDDR_H_
 
#include "gddr_telemetry_table.h"
#include "gddr_params.h"
 
#include <zephyr/sys/util.h>
#include <zephyr/sys_clock.h>
 
/* Oldest telemetry table version the SMC can still consume. Tables older than
 * GDDR_TELEMETRY_TABLE_T_VERSION simply lack the newer trailing fields.
 */
#define GDDR_TELEMETRY_TABLE_T_VERSION_MIN 2
 
/* gddr_params_table_t feature_bits fields (bh-mrisc feature_bit_t) */
#define GDDR_FEATURE_AC_TIMING_OVERRIDE       BIT(0)
#define GDDR_FEATURE_CTRL_PHY_PARAMS_OVERRIDE BIT(1)
#define GDDR_FEATURE_ENABLE_INLINE_ECC        BIT(2)
#define GDDR_FEATURE_CA_SETTINGS_VALID        BIT(3)
#define GDDR_FEATURE_ENABLE_CA_MARGIN_CHECK   BIT(4)
#define GDDR_FEATURE_ENABLE_CA_SWEEP_FALLBACK BIT(5)
 
#define MIN_GDDR_SPEED             12000
#define MAX_GDDR_SPEED             20000
#define GDDR_SPEED_TO_MEMCLK_RATIO 16
#define NUM_GDDR                   8
#define NUM_MRISC_NOC2AXI_PORT     3
 
/* MRISC FW telemetry base addr */
#define GDDR_TELEMETRY_TABLE_ADDR 0x8000
#define GDDR_MSG_STRUCT_ADDR      0x6000
 
#define RISC_CTRL_A_SCRATCH_0__REG_ADDR 0xFFB14010
#define RISC_CTRL_A_SCRATCH_1__REG_ADDR 0xFFB14014
#define RISC_CTRL_A_SCRATCH_2__REG_ADDR 0xFFB14018
#define MRISC_INIT_STATUS               RISC_CTRL_A_SCRATCH_0__REG_ADDR
#define MRISC_POST_CODE                 RISC_CTRL_A_SCRATCH_1__REG_ADDR
#define MRISC_MSG_REGISTER              RISC_CTRL_A_SCRATCH_2__REG_ADDR
 
#define MRISC_INIT_FINISHED 0xdeadbeef
#define MRISC_INIT_FAILED   0xfa11
#define MRISC_INIT_BEFORE   0x11111111
#define MRISC_INIT_STARTED  0x0
#ifdef CONFIG_TT_BH_ARC_GDDR_CA_LATCH
/* The CA sweep fallback (MRISC 2.17+) can escalate through the full
 * 15 VREFC x 4 termination x 8 driver strength matrix when no setting
 * satisfies the +/-N margin requirement. Measured worst case is ~28 s on a
 * P300 (failing points are dominated by training retries); allow for it.
 * Healthy boots still finish in well under a second - this only delays the
 * failure verdict for controllers that are already in trouble.
 */
#define MRISC_INIT_TIMEOUT 40000 /* In ms */
#else
#define MRISC_INIT_TIMEOUT 1000 /* In ms */
#endif
#define MRISC_MEMTEST_TIMEOUT          1000 /* In ms */
#define MRISC_POWER_SETTING_TIMEOUT_MS 1000
 
/* Defined by MRISC FW */

#define MRISC_MSG_TYPE_NONE          0
#define MRISC_MSG_TYPE_PHY_POWERDOWN 1
#define MRISC_MSG_TYPE_PHY_WAKEUP    2
#define MRISC_MSG_TYPE_RUN_MEMTEST   8
 
int read_gddr_telemetry_table(uint8_t gddr_inst, gddr_telemetry_table_t *gddr_telemetry);

struct gddr_inst_temp {
        uint8_t top;
        uint8_t bottom;
};

struct gddr_temps {
        uint32_t max_temp;                    /* degC, max across all read dies */
        struct gddr_inst_temp inst[NUM_GDDR]; /* per-instance top/bottom die temps */
};

int get_gddr_temps(struct gddr_temps *temps);

uint8_t get_gddr_mrisc_noc2axi_port(uint8_t gddr_inst);

struct gddr_bist_info {
        uint8_t complete;
        uint8_t failed;
};

struct gddr_bist_info get_gddr_bist_info(void);

int32_t set_mrisc_power_setting(bool on);
 
#endif