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TT-System-Firmware APIs 19.13.99
Tenstorrent Firmware
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#include "bh_reset.h"#include "gddr.h"#include "harvesting.h"#include "init.h"#include "noc.h"#include "noc_init.h"#include "noc2axi.h"#include "reg.h"#include "status_reg.h"#include <stddef.h>#include <tenstorrent/bh_power.h>#include <tenstorrent/msgqueue.h>#include <tenstorrent/post_code.h>#include <tenstorrent/smc_msg.h>#include <tenstorrent/spi_flash_buf.h>#include <tenstorrent/sys_init_defines.h>#include <tenstorrent/tt_boot_fs.h>#include <zephyr/drivers/misc/bh_fwtable.h>#include <zephyr/init.h>#include <zephyr/logging/log.h>#include <zephyr/kernel.h>#include <zephyr/device.h>#include <zephyr/devicetree.h>#include <zephyr/drivers/clock_control/clock_control_tt_bh.h>#include <zephyr/drivers/clock_control.h>#include <zephyr/drivers/dma.h>#include <zephyr/drivers/dma/dma_tt_bh_noc.h>#include <zephyr/drivers/dma/dma_arc_hs.h>
Macros | |
| #define | MRISC_FW_NOC2AXI_PORT 0 |
| #define | MRISC_SETUP_TLB 13 |
| #define | MRISC_L1_ADDR (1ULL << 37) |
| #define | MRISC_REG_ADDR (1ULL << 40) |
| #define | MRISC_FW_CFG_OFFSET 0x3C00 |
| #define | ARC_NOC0_X 8 |
| #define | ARC_NOC0_Y 0 |
| #define | MRISC_L1_SIZE (128 * 1024) |
| #define | MRISC_FW_TAG "memfw" |
| #define | MRISC_FW_CFG_TAG "memfwcfg" |
Functions | |
| uint8_t | get_gddr_mrisc_noc2axi_port (uint8_t gddr_inst) |
| Get the noc2axi port MRISC FW is loaded on for a GDDR instance. | |
| LOG_MODULE_REGISTER (gddr, CONFIG_TT_APP_LOG_LEVEL) | |
| struct gddr_bist_info | get_gddr_bist_info (void) |
| Get GDDR BIST status. | |
| static uint32_t | GetGddrSpeedFromCfg (uint8_t *fw_cfg_image) |
| static void | GetGddrMriscNocCoords (uint8_t gddr_inst, uint8_t noc_id, uint8_t *x, uint8_t *y) |
| static volatile void * | SetupMriscL1Tlb (uint8_t gddr_inst) |
| static uint32_t | MriscL1Read32 (uint8_t gddr_inst, uint32_t addr) |
| static void | MriscL1Write32 (uint8_t gddr_inst, uint32_t addr, uint32_t val) |
| static uint32_t | MriscRegRead32 (uint8_t gddr_inst, uint32_t addr) |
| static void | MriscRegWrite32 (uint8_t gddr_inst, uint32_t addr, uint32_t val) |
| int | read_gddr_telemetry_table (uint8_t gddr_inst, gddr_telemetry_table_t *gddr_telemetry) |
| static void | ReleaseMriscReset (uint8_t gddr_inst) |
| static void | SetAxiEnable (uint8_t gddr_inst, uint8_t noc2axi_port, bool axi_enable) |
| static int | LoadMriscFw (uint8_t gddr_inst, uint8_t *buf, size_t buf_size, size_t spi_address, size_t image_size) |
| static int | LoadMriscFwCfg (uint8_t gddr_inst, uint8_t *buf, size_t buf_size, size_t spi_address, size_t image_size) |
| static uint32_t | GetDramMask (void) |
| static int | read_gddr_temperature (uint8_t gddr_inst, struct gddr_inst_temp *temp) |
| int | get_gddr_temps (struct gddr_temps *temps) |
| Read the DRAM die temperatures for all enabled GDDR instances. | |
| static int | check_mrisc_busy (uint8_t gddr_inst) |
| static int | wait_mrisc_not_busy (uint8_t gddr_inst, k_timepoint_t timeout, const char *op_desc) |
| static int | StartHwMemtest (uint8_t gddr_inst, uint32_t addr_bits, uint32_t start_addr, uint32_t mask) |
| static int | CheckHwMemtestResult (uint8_t gddr_inst, k_timepoint_t timeout) |
| static void | wipe_l1 (void) |
| static int | InitMrisc (void) |
| SYS_INIT_APP (InitMrisc) | |
| static int | CheckGddrTraining (uint8_t gddr_inst, k_timepoint_t timeout) |
| static int | CheckGddrHwTest (void) |
| static int | gddr_training (void) |
| static int32_t | mrisc_message (uint32_t op_code, uint32_t instance_mask, uint32_t timeout_ms, const char *op_desc) |
| int32_t | set_mrisc_power_setting (bool on) |
| Sets the MRISC power setting for all active MRISCs. | |
| SYS_INIT_APP (gddr_training) | |
| static void | assert_mrisc_soft_reset (uint8_t gddr_inst) |
| static uint8_t | toggle_gddr_reset (const union request *req, struct response *rsp) |
| Toggle GDDR MRISC reset, re-train, and re-run BIST. | |
| REGISTER_MESSAGE (TT_SMC_MSG_TOGGLE_GDDR_RESET, toggle_gddr_reset) | |
Variables | |
| static const struct device *const | pll_dev_3 = DEVICE_DT_GET_OR_NULL(DT_NODELABEL(pll3)) |
| static const struct device * | flash = DEVICE_DT_GET_OR_NULL(DT_NODELABEL(spi_flash)) |
| static const struct device * | dma_noc = DEVICE_DT_GET(DT_NODELABEL(dma1)) |
| static const struct device *const | fwtable_dev = DEVICE_DT_GET(DT_NODELABEL(fwtable)) |
| static struct gddr_bist_info | gddr_bist |
| static uint8_t | gddr_telemetry_version_ok |
| #define ARC_NOC0_X 8 |
| #define ARC_NOC0_Y 0 |
| #define MRISC_FW_CFG_OFFSET 0x3C00 |
| #define MRISC_FW_CFG_TAG "memfwcfg" |
| #define MRISC_FW_NOC2AXI_PORT 0 |
| #define MRISC_FW_TAG "memfw" |
| #define MRISC_L1_ADDR (1ULL << 37) |
| #define MRISC_L1_SIZE (128 * 1024) |
| #define MRISC_REG_ADDR (1ULL << 40) |
| #define MRISC_SETUP_TLB 13 |
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| struct gddr_bist_info get_gddr_bist_info | ( | void | ) |
Get GDDR BIST status.
Get the noc2axi port MRISC FW is loaded on for a GDDR instance.
| [in] | gddr_inst | GDDR controller instance (0 - NUM_GDDR - 1). |
| int get_gddr_temps | ( | struct gddr_temps * | temps | ) |
Read the DRAM die temperatures for all enabled GDDR instances.
Disabled instances are left zeroed. Reads that fail are logged and skipped, leaving the corresponding entry zeroed while the remaining instances are still read.
| [out] | temps | Destination struct. Fully overwritten on entry. |
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| LOG_MODULE_REGISTER | ( | gddr | , |
| CONFIG_TT_APP_LOG_LEVEL | ) |
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| int read_gddr_telemetry_table | ( | uint8_t | gddr_inst, |
| gddr_telemetry_table_t * | gddr_telemetry ) |
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| REGISTER_MESSAGE | ( | TT_SMC_MSG_TOGGLE_GDDR_RESET | , |
| toggle_gddr_reset | ) |
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Sets the MRISC power setting for all active MRISCs.
| [in] | on | true to send MRISCs the MRISC_MSG_TYPE_PHY_WAKEUP command false to send MRISCs the MRISC_MSG_TYPE_PHY_POWERDOWN command |
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| SYS_INIT_APP | ( | gddr_training | ) |
| SYS_INIT_APP | ( | InitMrisc | ) |
Toggle GDDR MRISC reset, re-train, and re-run BIST.
Sequence: 1) Assert MRISC soft reset 2) Release MRISC reset 3) Wait for GDDR training completion 4) Re-run BIST 5) If PHY was powered down, issue PHY wakeup
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