TT-System-Firmware APIs 19.10.99
Tenstorrent Firmware
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pvt_tt_bh_rtio.c File Reference
#include <zephyr/drivers/sensor/tenstorrent/pvt_tt_bh.h>
#include <zephyr/drivers/sensor.h>
#include <zephyr/logging/log.h>
#include <zephyr/rtio/rtio.h>
#include <zephyr/rtio/work.h>
#include "functional_efuse.h"
Include dependency graph for pvt_tt_bh_rtio.c:

Data Structures

struct  ip_data_reg_t
union  ip_data_reg_u
struct  pvt_cntl_ts_pd_sdif_data_reg_t
union  pvt_cntl_ts_pd_sdif_data_reg_u
struct  pd_ip_cfg0_t
union  pd_ip_cfg0_u
struct  pvt_cntl_sdif_reg_t
union  pvt_cntl_sdif_reg_u
struct  pvt_cntl_sdif_status_reg_t
union  pvt_cntl_sdif_status_reg_u

Macros

#define SDIF_DONE_TIMEOUT_MS   10
#define TS_PD_OFFSET   0x40
#define VM_OFFSET   0x200
#define GET_TS_REG_ADDR(ID, REG_NAME)
#define GET_PD_REG_ADDR(ID, REG_NAME)
#define GET_VM_REG_ADDR(ID, REG_NAME)
#define ALL_AGING_OSC   0x7 /* enable delay chain 19, 20, 21 for aging measurement */
#define IP_CFG0_ADDR   0x1
#define IP_CNTL_ADDR   0x0
#define PVT_CNTL_IRQ_EN_REG_ADDR   0x80080040
#define PVT_CNTL_TS_00_IRQ_ENABLE_REG_ADDR   0x800800C0
#define PVT_CNTL_PD_00_IRQ_ENABLE_REG_ADDR   0x80080340
#define PVT_CNTL_VM_00_IRQ_ENABLE_REG_ADDR   0x80080A00
#define PVT_CNTL_TS_00_ALARMA_CFG_REG_ADDR   0x800800E0
#define PVT_CNTL_TS_00_ALARMB_CFG_REG_ADDR   0x800800E4
#define PVT_CNTL_TS_CMN_CLK_SYNTH_REG_ADDR   0x80080080
#define PVT_CNTL_PD_CMN_CLK_SYNTH_REG_ADDR   0x80080300
#define PVT_CNTL_VM_CMN_CLK_SYNTH_REG_ADDR   0x80080800
#define PVT_CNTL_PD_CMN_SDIF_STATUS_REG_ADDR   0x80080308
#define PVT_CNTL_PD_CMN_SDIF_REG_ADDR   0x8008030C
#define PVT_CNTL_TS_CMN_SDIF_STATUS_REG_ADDR   0x80080088
#define PVT_CNTL_TS_CMN_SDIF_REG_ADDR   0x8008008C
#define PVT_CNTL_PD_CMN_SDIF_STATUS_REG_ADDR   0x80080308
#define PVT_CNTL_PD_CMN_SDIF_REG_ADDR   0x8008030C
#define PVT_CNTL_VM_CMN_SDIF_STATUS_REG_ADDR   0x80080808
#define PVT_CNTL_VM_CMN_SDIF_REG_ADDR   0x8008080C
#define PVT_CNTL_TS_00_SDIF_DONE_REG_ADDR   0x800800D4
#define PVT_CNTL_TS_00_SDIF_DATA_REG_ADDR   0x800800D8
#define PVT_CNTL_VM_00_SDIF_RDATA_REG_ADDR   0x80080A30
#define PVT_CNTL_PD_00_SDIF_DONE_REG_ADDR   0x80080354
#define PVT_CNTL_PD_00_SDIF_DATA_REG_ADDR   0x80080358

Enumerations

enum  PvtType {
  TS = 0 ,
  PD = 1 ,
  VM = 2
}
enum  SampleType {
  ValidData = 0 ,
  AnalogueAccess = 1
}

Functions

 LOG_MODULE_DECLARE (pvt_tt_bh)
static void wait_sdif_ready (uint32_t status_reg_addr)
static void sdif_write (uint32_t status_reg_addr, uint32_t wr_data_reg_addr, uint32_t sdif_addr, uint32_t data)
static void select_delay_chain_and_start_pd_conv (uint32_t delay_chain)
static uint32_t get_pvt_addr (PvtType type, uint32_t id, uint32_t base_addr)
static ReadStatus read_pvt_auto_mode (PvtType type, uint32_t id, uint16_t *data, uint32_t sdif_done_base_addr, uint32_t sdif_data_base_addr)
static ReadStatus read_ts (const struct device *dev, uint8_t chan, uint16_t *data)
static ReadStatus read_ts_avg (const struct device *dev, uint16_t *sum)
static ReadStatus read_vm (uint32_t id, uint16_t *data)
static ReadStatus read_pd (uint32_t id, uint32_t delay_chain, uint16_t *data)
static void pvt_tt_bh_submit_sample (struct rtio_iodev_sqe *iodev_sqe)
void pvt_tt_bh_submit (const struct device *sensor, struct rtio_iodev_sqe *sqe)
void pvt_tt_bh_delay_chain_set (uint32_t new_delay_chain_)

Variables

static uint32_t selected_pd_delay_chain = 0xFF
static uint32_t new_delay_chain = 1

Macro Definition Documentation

◆ ALL_AGING_OSC

#define ALL_AGING_OSC   0x7 /* enable delay chain 19, 20, 21 for aging measurement */

◆ GET_PD_REG_ADDR

#define GET_PD_REG_ADDR ( ID,
REG_NAME )
Value:
(ID * TS_PD_OFFSET + PVT_CNTL_PD_00_##REG_NAME##_REG_ADDR)
TS_PD_OFFSET
#define TS_PD_OFFSET
Definition pvt_tt_bh.c:57

◆ GET_TS_REG_ADDR

#define GET_TS_REG_ADDR ( ID,
REG_NAME )
Value:
(ID * TS_PD_OFFSET + PVT_CNTL_TS_00_##REG_NAME##_REG_ADDR)

◆ GET_VM_REG_ADDR

#define GET_VM_REG_ADDR ( ID,
REG_NAME )
Value:
(ID * VM_OFFSET + PVT_CNTL_VM_00_##REG_NAME##_REG_ADDR)
VM_OFFSET
#define VM_OFFSET
Definition pvt_tt_bh.c:58

◆ IP_CFG0_ADDR

#define IP_CFG0_ADDR   0x1

◆ IP_CNTL_ADDR

#define IP_CNTL_ADDR   0x0

◆ PVT_CNTL_IRQ_EN_REG_ADDR

#define PVT_CNTL_IRQ_EN_REG_ADDR   0x80080040

◆ PVT_CNTL_PD_00_IRQ_ENABLE_REG_ADDR

#define PVT_CNTL_PD_00_IRQ_ENABLE_REG_ADDR   0x80080340

◆ PVT_CNTL_PD_00_SDIF_DATA_REG_ADDR

#define PVT_CNTL_PD_00_SDIF_DATA_REG_ADDR   0x80080358

◆ PVT_CNTL_PD_00_SDIF_DONE_REG_ADDR

#define PVT_CNTL_PD_00_SDIF_DONE_REG_ADDR   0x80080354

◆ PVT_CNTL_PD_CMN_CLK_SYNTH_REG_ADDR

#define PVT_CNTL_PD_CMN_CLK_SYNTH_REG_ADDR   0x80080300

◆ PVT_CNTL_PD_CMN_SDIF_REG_ADDR [1/2]

#define PVT_CNTL_PD_CMN_SDIF_REG_ADDR   0x8008030C

◆ PVT_CNTL_PD_CMN_SDIF_REG_ADDR [2/2]

#define PVT_CNTL_PD_CMN_SDIF_REG_ADDR   0x8008030C

◆ PVT_CNTL_PD_CMN_SDIF_STATUS_REG_ADDR [1/2]

#define PVT_CNTL_PD_CMN_SDIF_STATUS_REG_ADDR   0x80080308

◆ PVT_CNTL_PD_CMN_SDIF_STATUS_REG_ADDR [2/2]

#define PVT_CNTL_PD_CMN_SDIF_STATUS_REG_ADDR   0x80080308

◆ PVT_CNTL_TS_00_ALARMA_CFG_REG_ADDR

#define PVT_CNTL_TS_00_ALARMA_CFG_REG_ADDR   0x800800E0

◆ PVT_CNTL_TS_00_ALARMB_CFG_REG_ADDR

#define PVT_CNTL_TS_00_ALARMB_CFG_REG_ADDR   0x800800E4

◆ PVT_CNTL_TS_00_IRQ_ENABLE_REG_ADDR

#define PVT_CNTL_TS_00_IRQ_ENABLE_REG_ADDR   0x800800C0

◆ PVT_CNTL_TS_00_SDIF_DATA_REG_ADDR

#define PVT_CNTL_TS_00_SDIF_DATA_REG_ADDR   0x800800D8

◆ PVT_CNTL_TS_00_SDIF_DONE_REG_ADDR

#define PVT_CNTL_TS_00_SDIF_DONE_REG_ADDR   0x800800D4

◆ PVT_CNTL_TS_CMN_CLK_SYNTH_REG_ADDR

#define PVT_CNTL_TS_CMN_CLK_SYNTH_REG_ADDR   0x80080080

◆ PVT_CNTL_TS_CMN_SDIF_REG_ADDR

#define PVT_CNTL_TS_CMN_SDIF_REG_ADDR   0x8008008C

◆ PVT_CNTL_TS_CMN_SDIF_STATUS_REG_ADDR

#define PVT_CNTL_TS_CMN_SDIF_STATUS_REG_ADDR   0x80080088

◆ PVT_CNTL_VM_00_IRQ_ENABLE_REG_ADDR

#define PVT_CNTL_VM_00_IRQ_ENABLE_REG_ADDR   0x80080A00

◆ PVT_CNTL_VM_00_SDIF_RDATA_REG_ADDR

#define PVT_CNTL_VM_00_SDIF_RDATA_REG_ADDR   0x80080A30

◆ PVT_CNTL_VM_CMN_CLK_SYNTH_REG_ADDR

#define PVT_CNTL_VM_CMN_CLK_SYNTH_REG_ADDR   0x80080800

◆ PVT_CNTL_VM_CMN_SDIF_REG_ADDR

#define PVT_CNTL_VM_CMN_SDIF_REG_ADDR   0x8008080C

◆ PVT_CNTL_VM_CMN_SDIF_STATUS_REG_ADDR

#define PVT_CNTL_VM_CMN_SDIF_STATUS_REG_ADDR   0x80080808

◆ SDIF_DONE_TIMEOUT_MS

#define SDIF_DONE_TIMEOUT_MS   10

◆ TS_PD_OFFSET

#define TS_PD_OFFSET   0x40

◆ VM_OFFSET

#define VM_OFFSET   0x200

Enumeration Type Documentation

◆ PvtType

enum PvtType
Enumerator
TS 0 
PD 1 
VM 2 

◆ SampleType

enum SampleType
Enumerator
ValidData 0 
AnalogueAccess 1 

Function Documentation

◆ get_pvt_addr()

uint32_t get_pvt_addr ( PvtType type,
uint32_t id,
uint32_t base_addr )
static

◆ LOG_MODULE_DECLARE()

LOG_MODULE_DECLARE ( pvt_tt_bh )

◆ pvt_tt_bh_delay_chain_set()

void pvt_tt_bh_delay_chain_set ( uint32_t new_delay_chain_)

◆ pvt_tt_bh_submit()

void pvt_tt_bh_submit ( const struct device * sensor,
struct rtio_iodev_sqe * sqe )

◆ pvt_tt_bh_submit_sample()

void pvt_tt_bh_submit_sample ( struct rtio_iodev_sqe * iodev_sqe)
static

◆ read_pd()

ReadStatus read_pd ( uint32_t id,
uint32_t delay_chain,
uint16_t * data )
static

◆ read_pvt_auto_mode()

ReadStatus read_pvt_auto_mode ( PvtType type,
uint32_t id,
uint16_t * data,
uint32_t sdif_done_base_addr,
uint32_t sdif_data_base_addr )
static

◆ read_ts()

ReadStatus read_ts ( const struct device * dev,
uint8_t chan,
uint16_t * data )
static

◆ read_ts_avg()

ReadStatus read_ts_avg ( const struct device * dev,
uint16_t * sum )
static

◆ read_vm()

ReadStatus read_vm ( uint32_t id,
uint16_t * data )
static

◆ sdif_write()

void sdif_write ( uint32_t status_reg_addr,
uint32_t wr_data_reg_addr,
uint32_t sdif_addr,
uint32_t data )
static

◆ select_delay_chain_and_start_pd_conv()

void select_delay_chain_and_start_pd_conv ( uint32_t delay_chain)
static

◆ wait_sdif_ready()

void wait_sdif_ready ( uint32_t status_reg_addr)
static

Variable Documentation

◆ new_delay_chain

uint32_t new_delay_chain = 1
static

◆ selected_pd_delay_chain

uint32_t selected_pd_delay_chain = 0xFF
static