tt_d2d.c File Reference

#include <zephyr/device.h>
#include <zephyr/drivers/dma.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/logging/log.h>
#include <d2d_api_driver.h>
#include <d2d_api_fw_progress_codes.h>
#include <d2d_api_general_definitions.h>
#include <platform.h>
#include <zephyr/drivers/misc/tt_d2d.h>

Include dependency graph for tt_d2d.c:

Data Structures
struct	tt_d2d_config

Macros
#define	DT_DRV_COMPAT   tenstorrent_grendel_d2d
#define	TT_D2D_OFFSET(addr)
#define	TT_D2D_STRAP_RESET_OFFSET   TT_D2D_OFFSET(D2D_0_STRAP_RESET_REG_ADDR)
#define	TT_D2D_CPU_CTRL_OFFSET   TT_D2D_OFFSET(D2D_0_D2D_D2D_SS_ASYNC_CPU_CTRL_REG_ADDR)
#define	TT_D2D_SRAM_OFFSET   TT_D2D_OFFSET(D2D_0_D2D_D2D_ROCKET_REG_MAP_BASE_ADDR)
#define	TT_D2D_CFG_OFFSET   ((uint32_t)(HOST_CONFIGURATION_AVAILABLE_REG - D2D_MEMORY_BASE))
#define	TT_D2D_CFG_PARM_OFFSET(parm)
#define	TT_D2D_CFG_END   TT_D2D_CFG_PARM_OFFSET(RECOVERY_MODE + 1)
#define	TT_D2D_IMAGE_MAX   TT_D2D_CFG_OFFSET
#define	TT_D2D_PROGRESS_CODE_OFFSET   ((uint32_t)(DMEM_PROGRESS_CODE_REG - D2D_MEMORY_BASE))
#define	TT_D2D_SRAM_USED_END   (TT_D2D_PROGRESS_CODE_OFFSET + sizeof(uint32_t))
#define	TT_D2D_LINK_POLL_INTERVAL_US   100U
#define	TT_D2D_LPBK2_RX_SLICE   4U
#define	TT_D2D_LPBK2_MEM_PATTERN   0xABCDU
#define	TT_D2D_PROBE_PATTERN   0xD2D0F00DU
#define	TT_D2D_ZERO_BLOCK   4096U
#define	TT_D2D_DMA_DEV(inst)
#define	TT_D2D_DMA_CHANNEL(inst)
#define	TT_D2D_INIT(inst)

Functions
	LOG_MODULE_REGISTER (tt_d2d, CONFIG_TT_D2D_LOG_LEVEL)
	BUILD_ASSERT (D2D_1_STRAP_RESET_REG_ADDR - D2D_1_REG_MAP_BASE_ADDR==((D2D_0_STRAP_RESET_REG_ADDR) - D2D_0_REG_MAP_BASE_ADDR) &&D2D_1_D2D_D2D_SS_ASYNC_CPU_CTRL_REG_ADDR - D2D_1_REG_MAP_BASE_ADDR==((D2D_0_D2D_D2D_SS_ASYNC_CPU_CTRL_REG_ADDR) - D2D_0_REG_MAP_BASE_ADDR) &&D2D_1_D2D_D2D_ROCKET_REG_MAP_BASE_ADDR - D2D_1_REG_MAP_BASE_ADDR==((D2D_0_D2D_D2D_ROCKET_REG_MAP_BASE_ADDR) - D2D_0_REG_MAP_BASE_ADDR), "every D2D tile must share one register layout for base-relative offsets to hold")
	BUILD_ASSERT (D2D_MEMORY_BASE==((D2D_0_D2D_D2D_ROCKET_REG_MAP_BASE_ADDR) - D2D_0_REG_MAP_BASE_ADDR), "the D2D API memory map and the register map disagree on the SRAM window")
	BUILD_ASSERT ((((uint32_t)(DMEM_PROGRESS_CODE_REG - D2D_MEMORY_BASE))+sizeof(uint32_t))>((uint32_t)((HOST_CONFIGURATION_START - D2D_MEMORY_BASE)+((RECOVERY_MODE+1) *sizeof(uint32_t)))), "the progress code is assumed to be the highest SRAM word the driver touches")
static uint32_t	tt_d2d_cpu_ctrl (bool run_core)
static uint64_t tt_d2d_zero_page[4096U/sizeof(uint64_t)]	__aligned (4096U)
static uintptr_t	tt_d2d_sram (const struct tt_d2d_config *config)
static void	tt_d2d_cfg_write (const struct tt_d2d_config *config, tCONFIG_PARM parm, uint32_t value)
int	tt_d2d_reset_release (const struct device *dev)
	Deassert a D2D tile's subsystem resets, in hardware order.
static int	tt_d2d_dma_run (const struct device *dev, uintptr_t src, uintptr_t dst, uint32_t len, uint32_t src_stride, uint32_t dst_stride, uint32_t repetitions)
static int	tt_d2d_clear_sram (const struct device *dev, uintptr_t sram)
static int	tt_d2d_copy_image (const struct device *dev, uintptr_t sram, const uint8_t *img, size_t img_size)
static void	tt_d2d_write_config (const struct device *dev)
int	tt_d2d_load_fw (const struct device *dev, const uint8_t *img, size_t img_size)
	Load firmware into a D2D tile, leaving the Rocket halted.
int	tt_d2d_start (const struct device *dev)
	Release a D2D tile's Rocket so loaded firmware begins executing.
uint32_t	tt_d2d_progress_code (const struct device *dev)
	Firmware training progress code (drop d2d_api_fw_progress_codes.h).
int	tt_d2d_wait_link (const struct device *dev, k_timeout_t timeout)
	Wait for this end of the link to finish training.
static int	tt_d2d_init (const struct device *dev)

Macro Definition Documentation

DT_DRV_COMPAT

#define DT_DRV_COMPAT   tenstorrent_grendel_d2d

TT_D2D_CFG_END

#define TT_D2D_CFG_END   TT_D2D_CFG_PARM_OFFSET(RECOVERY_MODE + 1)

TT_D2D_CFG_OFFSET

#define TT_D2D_CFG_OFFSET   ((uint32_t)(HOST_CONFIGURATION_AVAILABLE_REG - D2D_MEMORY_BASE))

TT_D2D_CFG_PARM_OFFSET

#define TT_D2D_CFG_PARM_OFFSET

(

parm

)

Value:

        ((uint32_t)((HOST_CONFIGURATION_START - D2D_MEMORY_BASE) + ((parm) * sizeof(uint32_t))))

TT_D2D_CPU_CTRL_OFFSET

#define TT_D2D_CPU_CTRL_OFFSET   TT_D2D_OFFSET(D2D_0_D2D_D2D_SS_ASYNC_CPU_CTRL_REG_ADDR)

TT_D2D_DMA_CHANNEL

#define TT_D2D_DMA_CHANNEL

(

inst

)

Value:

        COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, dmas),                                             \
                    (DT_INST_DMAS_CELL_BY_IDX(inst, 0, channel)), (0))

TT_D2D_DMA_DEV

#define TT_D2D_DMA_DEV

(

inst

)

Value:

        COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, dmas),                                             \
                    (DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_IDX(inst, 0))), (NULL))

TT_D2D_IMAGE_MAX

#define TT_D2D_IMAGE_MAX   TT_D2D_CFG_OFFSET

TT_D2D_INIT

#define TT_D2D_INIT

(

inst

)

Value:

        static const struct tt_d2d_config tt_d2d_config_##inst = {                                 \
                .base = DT_INST_REG_ADDR(inst),                                                    \
                .dma_dev = TT_D2D_DMA_DEV(inst),                                                   \
                .dma_channel = TT_D2D_DMA_CHANNEL(inst),                                           \
                .sram_size = DT_INST_PROP(inst, sram_size),                                        \
                .bits_per_channel = DT_INST_PROP(inst, bits_per_channel),                          \
                .refclk_period_ns = DT_INST_PROP(inst, refclk_period_ns),                          \
                .apb_clk_period_ps = DT_INST_PROP(inst, apb_clk_period_ps),                        \
                .pll_freq_ghz = DT_INST_PROP(inst, pll_freq_ghz),                                  \
                .package_type_this_die = DT_INST_PROP(inst, package_type_this_die),                \
                .package_type_other_die = DT_INST_PROP(inst, package_type_other_die),              \
                .bypass_phy = DT_INST_PROP(inst, bypass_phy),                                      \
                .bypass_vreg = DT_INST_PROP(inst, bypass_vreg),                                    \
                .disable_sideband = DT_INST_PROP(inst, disable_sideband),                          \
        };                                                                                         \
                                                                                                   \
        DEVICE_DT_INST_DEFINE(inst, tt_d2d_init, NULL, NULL, &tt_d2d_config_##inst, POST_KERNEL,   \
                              CONFIG_TT_D2D_INIT_PRIO, NULL);

TT_D2D_LINK_POLL_INTERVAL_US

#define TT_D2D_LINK_POLL_INTERVAL_US   100U

TT_D2D_LPBK2_MEM_PATTERN

#define TT_D2D_LPBK2_MEM_PATTERN   0xABCDU

TT_D2D_LPBK2_RX_SLICE

#define TT_D2D_LPBK2_RX_SLICE   4U

TT_D2D_OFFSET

#define TT_D2D_OFFSET

(

addr

)

Value:

((addr) - D2D_0_REG_MAP_BASE_ADDR)

TT_D2D_PROBE_PATTERN

#define TT_D2D_PROBE_PATTERN   0xD2D0F00DU

TT_D2D_PROGRESS_CODE_OFFSET

#define TT_D2D_PROGRESS_CODE_OFFSET   ((uint32_t)(DMEM_PROGRESS_CODE_REG - D2D_MEMORY_BASE))

TT_D2D_SRAM_OFFSET

#define TT_D2D_SRAM_OFFSET   TT_D2D_OFFSET(D2D_0_D2D_D2D_ROCKET_REG_MAP_BASE_ADDR)

TT_D2D_SRAM_USED_END

#define TT_D2D_SRAM_USED_END   (TT_D2D_PROGRESS_CODE_OFFSET + sizeof(uint32_t))

TT_D2D_STRAP_RESET_OFFSET

#define TT_D2D_STRAP_RESET_OFFSET   TT_D2D_OFFSET(D2D_0_STRAP_RESET_REG_ADDR)

TT_D2D_ZERO_BLOCK

#define TT_D2D_ZERO_BLOCK   4096U

Function Documentation

__aligned()

uint64_t tt_d2d_zero_page[4096U/sizeof(uint64_t)] __aligned ( 4096U )

static

BUILD_ASSERT() [1/3]

BUILD_ASSERT	(	(((uint32_t)(DMEM_PROGRESS_CODE_REG - D2D_MEMORY_BASE))+sizeof(uint32_t))	,
		((uint32_t)((HOST_CONFIGURATION_START - D2D_MEMORY_BASE)+((RECOVERY_MODE+1) *sizeof(uint32_t))))	,
		"the progress code is assumed to be the highest SRAM word the driver touches"	)

BUILD_ASSERT() [2/3]

BUILD_ASSERT	(	D2D_1_STRAP_RESET_REG_ADDR -	D2D_1_REG_MAP_BASE_ADDR = =((D2D_0_STRAP_RESET_REG_ADDR) - D2D_0_REG_MAP_BASE_ADDR) &&D2D_1_D2D_D2D_SS_ASYNC_CPU_CTRL_REG_ADDR - D2D_1_REG_MAP_BASE_ADDR==((D2D_0_D2D_D2D_SS_ASYNC_CPU_CTRL_REG_ADDR) - D2D_0_REG_MAP_BASE_ADDR) &&D2D_1_D2D_D2D_ROCKET_REG_MAP_BASE_ADDR - D2D_1_REG_MAP_BASE_ADDR==((D2D_0_D2D_D2D_ROCKET_REG_MAP_BASE_ADDR) - D2D_0_REG_MAP_BASE_ADDR),
		"every D2D tile must share one register layout for base-relative offsets to hold"	)

BUILD_ASSERT() [3/3]

BUILD_ASSERT	(	D2D_MEMORY_BASE	= =((D2D_0_D2D_D2D_ROCKET_REG_MAP_BASE_ADDR) - D2D_0_REG_MAP_BASE_ADDR),
		"the D2D API memory map and the register map disagree on the SRAM window"	)

LOG_MODULE_REGISTER()

LOG_MODULE_REGISTER	(	tt_d2d	,
		CONFIG_TT_D2D_LOG_LEVEL	)

tt_d2d_cfg_write()

void tt_d2d_cfg_write ( const struct tt_d2d_config * config, tCONFIG_PARM parm, uint32_t value )

inlinestatic

tt_d2d_clear_sram()

int tt_d2d_clear_sram ( const struct device * dev, uintptr_t sram )

static

tt_d2d_copy_image()

int tt_d2d_copy_image ( const struct device * dev, uintptr_t sram, const uint8_t * img, size_t img_size )

static

tt_d2d_cpu_ctrl()

uint32_t tt_d2d_cpu_ctrl ( bool run_core )

inlinestatic

tt_d2d_dma_run()

int tt_d2d_dma_run ( const struct device * dev, uintptr_t src, uintptr_t dst, uint32_t len, uint32_t src_stride, uint32_t dst_stride, uint32_t repetitions )

static

tt_d2d_init()

int tt_d2d_init ( const struct device * dev )

static

tt_d2d_load_fw()

int tt_d2d_load_fw	(	const struct device *	dev,
		const uint8_t *	img,
		size_t	img_size )

Load firmware into a D2D tile, leaving the Rocket halted.

Parameters

dev	D2D tile device
img	Firmware image
img_size	Size of img in bytes. Multiple of 4; must not overrun the configuration block at the top of SRAM.

Return values

0	on success
-EINVAL	if img is NULL, empty, or not a multiple of 4 bytes
-ENOSPC	if img would overrun the configuration block
-ENODEV	if the tile does not answer a write to its SRAM
-EIO	if the image read back from SRAM does not match img

tt_d2d_progress_code()

uint32_t tt_d2d_progress_code

(

const struct device *

dev

)

Firmware training progress code (drop d2d_api_fw_progress_codes.h).

Parameters

dev	D2D tile device

Returns

the firmware's current progress code, or 0 if none yet

tt_d2d_reset_release()

int tt_d2d_reset_release

(

const struct device *

dev

)

Deassert a D2D tile's subsystem resets, in hardware order.

Parameters

dev	D2D tile device

Return values

0	on success

tt_d2d_sram()

uintptr_t tt_d2d_sram ( const struct tt_d2d_config * config )

inlinestatic

tt_d2d_start()

int tt_d2d_start

(

const struct device *

dev

)

Release a D2D tile's Rocket so loaded firmware begins executing.

Parameters

dev	D2D tile device

Return values

0	on success

tt_d2d_wait_link()

int tt_d2d_wait_link	(	const struct device *	dev,
		k_timeout_t	timeout )

Wait for this end of the link to finish training.

Polls the firmware progress code in SRAM (link-layer status is not modelled on emu). Both ends must already have been started.

Parameters

dev	D2D tile device
timeout	How long to wait, or K_FOREVER

Return values

0	if the link trained
-EIO	if the firmware reported a training failure
-ETIMEDOUT	if it did neither

tt_d2d_write_config()

void tt_d2d_write_config ( const struct device * dev )

static