ttnn.max_pool2d
This table is a trace for ttnn.max_pool2d op. Traces are generated from nightly tt-torch runs. To see nightly runs: Nightly Runs
| Name | Input Shapes | Input Layouts | Attributes | Output Shapes | Output Layouts | PCC | ATOL |
|---|---|---|---|---|---|---|---|
| ttnn.max_pool2d | tensor<[1,1,784,16,bf16]> | mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 784 + d1 * 784 + d2, d3), memory_config: (784, 16, 'bf16', 'dram') | batch_size: 1 : si32 ceil_mode: False channels: 16 : si32 dilation: array<i32: 1, 1> input_height: 28 : si32 input_width: 28 : si32 kernel_size: array<i32: 2, 2> padding: array<i32: 0, 0> stride: array<i32: 2, 2> | tensor<[1,1,196,16,bf16]> | mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 196 + d1 * 196 + d2, d3), memory_config: (196, 16, 'bf16', 'dram') | nan | nan |
| ttnn.max_pool2d | tensor<[1,1,196,4,bf16]> | mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 196 + d1 * 196 + d2, d3), memory_config: (196, 4, 'bf16', 'dram') | batch_size: 1 : si32 ceil_mode: False channels: 4 : si32 dilation: array<i32: 1, 1> input_height: 14 : si32 input_width: 14 : si32 kernel_size: array<i32: 2, 2> padding: array<i32: 0, 0> stride: array<i32: 2, 2> | tensor<[1,1,49,4,bf16]> | mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 49 + d1 * 49 + d2, d3), memory_config: (49, 4, 'bf16', 'dram') | nan | nan |
| ttnn.max_pool2d | tensor<[1,1,196,528,bf16]> | mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 196 + d1 * 196 + d2, d3), memory_config: (196, 528, 'bf16', 'dram') | batch_size: 1 : si32 ceil_mode: False channels: 528 : si32 dilation: array<i32: 1, 1> input_height: 14 : si32 input_width: 14 : si32 kernel_size: array<i32: 3, 3> padding: array<i32: 1, 1> stride: array<i32: 1, 1> | tensor<[1,1,196,528,bf16]> | mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 196 + d1 * 196 + d2, d3), memory_config: (196, 528, 'bf16', 'dram') | nan | nan |