Here is a list of all struct and union fields with links to the structures/unions they belong to:

- r -

• raie : BH_PCIE_DWC_PCIE_USP_PF0_HDMA_CAP_HDMA_INT_SETUP_OFF_RDCH_0_reg_t, BH_PCIE_DWC_PCIE_USP_PF0_HDMA_CAP_HDMA_INT_SETUP_OFF_WRCH_0_reg_t
• raw : pvt_tt_bh_rtio_data
• raw_speed : force_fan_speed_rqst
• rcv_handler : SmbusCmdDef
• rd_req : DW_APB_I2C_IC_RAW_INTR_STAT_reg_t
• rdlh_link_up_sync : PCIE_SII_LTSSM_STATE_reg_t
• read_id : jtag_api
• refclk_cnt_en : RESET_UNIT_GLOBAL_RESET_reg_t
• refclk_disable : RESET_UNIT_CHIP_DEBUG_TRACE_IF_CNTL_reg_t
• refdiv : PLL_CNTL_PLL_CNTL_1_reg_t
• regulator_config : BoardRegulatorsConfig
• regulator_data : RegulatorConfig
• regulator_init_error : STATUS_ERROR_STATUS0_reg_t
• req_voltage : VoltageArbiter
• request_queue : message_queue
• request_queue_rptr : message_queue_header
• request_queue_wptr : message_queue_header
• reserved : OperationBits, power_setting_rqst
• reserved_1 : NOC2AXITlb2RegT
• reserved_2 : RESET_UNIT_PCIE_MISC_CNTL3_reg_t
• reserved_31_11 : RESET_UNIT_PCIE_MISC_CNTL3_reg_t
• reserved_7_31 : BH_PCIE_DWC_PCIE_USP_PF0_HDMA_CAP_HDMA_INT_SETUP_OFF_RDCH_0_reg_t, BH_PCIE_DWC_PCIE_USP_PF0_HDMA_CAP_HDMA_INT_SETUP_OFF_WRCH_0_reg_t
• reset : jtag_api, PLL_CNTL_PLL_CNTL_0_reg_t
• reset_lock : PLL_CNTL_PLL_CNTL_0_reg_t
• response_queue : message_queue
• response_queue_rptr : message_queue_header
• response_queue_wptr : message_queue_header
• restart_det : DW_APB_I2C_IC_RAW_INTR_STAT_reg_t
• ret : cm2dmMessageRet
• rfe : UART_ADDRESS_BLOCK_LSR_reg_t
• ro : PCIE_SII_NOC_TLB_DATA_reg_t
• rsie : BH_PCIE_DWC_PCIE_USP_PF0_HDMA_CAP_HDMA_INT_SETUP_OFF_RDCH_0_reg_t, BH_PCIE_DWC_PCIE_USP_PF0_HDMA_CAP_HDMA_INT_SETUP_OFF_WRCH_0_reg_t
• rsvd_0 : APB2AVSBUS_AVS_CFG_1_reg_t, CHIP_DEBUG_TRACE_CHIP_DEBUG_TRACE_BUFFER_INTR_CNTL_reg_t, CHIP_DEBUG_TRACE_CHIP_DEBUG_TRACE_CLIENT_FILTER_CNT_reg_t, CHIP_DEBUG_TRACE_CHIP_DEBUG_TRACE_REFCLK_COUNTER_CNTL_reg_t, DW_APB_I2C_IC_CON_reg_t, EFUSE_CNTL_EFUSE_RD_CNTL_reg_t, PCIE_SII_APP_PCIE_CTL_reg_t, PCIE_SII_NOC_TLB_DATA_reg_t, PMM_BLOCK_PMM_MESSAGE_reg_t, RESET_UNIT_ARC_MISC_CNTL_reg_t, RESET_UNIT_CATMON_THERM_TRIP_CNTL_reg_t, RESET_UNIT_ETH_RESET_reg_t, RESET_UNIT_GLOBAL_RESET_reg_t, RESET_UNIT_UART_CNTL_reg_t
• rsvd_1 : APB2AVSBUS_AVS_CFG_1_reg_t, EFUSE_CNTL_EFUSE_RD_CNTL_reg_t, RESET_UNIT_ARC_MISC_CNTL_reg_t, RESET_UNIT_GLOBAL_RESET_reg_t, RESET_UNIT_UART_CNTL_reg_t
• rsvd_2 : EFUSE_CNTL_EFUSE_RD_CNTL_reg_t
• rsvd_ic_con_1 : DW_APB_I2C_IC_CON_reg_t
• rsvd_ic_con_2 : DW_APB_I2C_IC_CON_reg_t
• rsvd_ic_raw_intr_stat : DW_APB_I2C_IC_RAW_INTR_STAT_reg_t
• rsvd_ic_sar2_smbus_arp_en : DW_APB_I2C_IC_CON_reg_t
• rsvd_ic_sar3_smbus_arp_en : DW_APB_I2C_IC_CON_reg_t
• rsvd_ic_sar4_smbus_arp_en : DW_APB_I2C_IC_CON_reg_t
• rsvd_iir_31to8 : UART_ADDRESS_BLOCK_IIR_reg_t
• rsvd_iir_5to4 : UART_ADDRESS_BLOCK_IIR_reg_t
• rsvd_lcr_31to8 : UART_ADDRESS_BLOCK_LCR_reg_t
• rsvd_lsr_31to9 : UART_ADDRESS_BLOCK_LSR_reg_t
• rsvd_optional_sar_ctrl : DW_APB_I2C_IC_CON_reg_t
• rsvd_slv_addr1_tag : DW_APB_I2C_IC_RAW_INTR_STAT_reg_t
• rsvd_slv_addr2_tag : DW_APB_I2C_IC_RAW_INTR_STAT_reg_t
• rsvd_slv_addr3_tag : DW_APB_I2C_IC_RAW_INTR_STAT_reg_t
• rsvd_slv_addr4_tag : DW_APB_I2C_IC_RAW_INTR_STAT_reg_t
• rsvd_wr_req : DW_APB_I2C_IC_RAW_INTR_STAT_reg_t
• rsvdp_27 : BH_PCIE_DWC_PCIE_USP_PF0_MSI_CAP_HDL_PATH_E982B20F_PCI_MSI_CAP_ID_NEXT_CTRL_REG_reg_t
• run : RESET_UNIT_ARC_MISC_CNTL_reg_t
• rx_ack : RESET_UNIT_UART_CNTL_reg_t
• rx_cap : tt_vuart
• rx_done : DW_APB_I2C_IC_RAW_INTR_STAT_reg_t
• rx_fifo_full_hld_ctrl : DW_APB_I2C_IC_CON_reg_t
• rx_full : DW_APB_I2C_IC_RAW_INTR_STAT_reg_t
• rx_head : tt_vuart
• rx_over : DW_APB_I2C_IC_RAW_INTR_STAT_reg_t
• rx_tail : tt_vuart
• rx_under : DW_APB_I2C_IC_RAW_INTR_STAT_reg_t