Field Documentation

◆ app_clk_req_n_axiclk

uint32_t PCIE_SII_APP_PCIE_CTL_reg_t::app_clk_req_n_axiclk

uint32_t PCIE_SII_APP_PCIE_CTL_reg_t::app_hold_phy_rst_axiclk

uint32_t PCIE_SII_APP_PCIE_CTL_reg_t::app_l1sub_disable_axiclk

uint32_t PCIE_SII_APP_PCIE_CTL_reg_t::app_margining_ready_axiclk

uint32_t PCIE_SII_APP_PCIE_CTL_reg_t::app_margining_software_ready_axiclk

uint32_t PCIE_SII_APP_PCIE_CTL_reg_t::app_pf_req_retry_en_axiclk

uint32_t PCIE_SII_APP_PCIE_CTL_reg_t::mstr_rasdp_err_mode

uint32_t PCIE_SII_APP_PCIE_CTL_reg_t::phy_clk_req_n_axiclk

uint32_t PCIE_SII_APP_PCIE_CTL_reg_t::rsvd_0

uint32_t PCIE_SII_APP_PCIE_CTL_reg_t::slv_rasdp_err_mode

The documentation for this struct was generated from the following file:

/home/runner/work/tt-zephyr-platforms/tt-zephyr-platforms/tt-zephyr-platforms/lib/tenstorrent/bh_arc/pcie.c

Data Fields
uint32_t	app_hold_phy_rst_axiclk: 1
uint32_t	app_l1sub_disable_axiclk: 1
uint32_t	app_margining_ready_axiclk: 1
uint32_t	app_margining_software_ready_axiclk: 1
uint32_t	app_pf_req_retry_en_axiclk: 1
uint32_t	app_clk_req_n_axiclk: 1
uint32_t	phy_clk_req_n_axiclk: 1
uint32_t	rsvd_0: 23
uint32_t	slv_rasdp_err_mode: 1
uint32_t	mstr_rasdp_err_mode: 1