TT Zephyr Platforms 18.11.99
Tenstorrent Firmware
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#include "cm2dm_msg.h"
#include "init.h"
#include "irqnum.h"
#include "noc2axi.h"
#include "pcie.h"
#include "pciesd.h"
#include "reg.h"
#include "status_reg.h"
#include "timer.h"
#include <stdbool.h>
#include <tenstorrent/post_code.h>
#include <tenstorrent/sys_init_defines.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/misc/bh_fwtable.h>
#include <zephyr/init.h>
#include <zephyr/sys/util.h>
Data Structures | |
struct | PCIE_SII_NOC_TLB_DATA_reg_t |
union | PCIE_SII_NOC_TLB_DATA_reg_u |
struct | PCIE_SII_APP_PCIE_CTL_reg_t |
union | PCIE_SII_APP_PCIE_CTL_reg_u |
struct | PCIE_SII_LTSSM_STATE_reg_t |
union | PCIE_SII_LTSSM_STATE_reg_u |
Functions | |
static void | WritePcieTlbConfigReg (const uint32_t addr, const uint32_t data) |
static void | WriteDbiRegByte (const uint32_t addr, const uint8_t data) |
static void | WriteSiiReg (const uint32_t addr, const uint32_t data) |
static uint32_t | ReadSiiReg (const uint32_t addr) |
static void | WriteSerdesAlphaCoreReg (const uint8_t inst, const uint32_t addr, const uint32_t data) |
static uint32_t | ReadSerdesAlphaCoreReg (const uint8_t inst, const uint32_t addr) |
static void | WriteSerdesCtrlReg (const uint8_t inst, const uint32_t addr, const uint32_t data) |
static void | SetupDbiAccess (void) |
static void | InitResetInterrupt (uint8_t pcie_inst) |
static void | SetupOutboundTlbs (void) |
static void | ConfigurePCIeTlbs (uint8_t pcie_inst) |
static void | SetupInboundTlbs (void) |
static void | SetupSii (void) |
static PCIeInitStatus | PCIeInitComm (uint8_t pcie_inst, uint8_t num_serdes_instance, PCIeDeviceType device_type, uint8_t max_pcie_speed) |
static void | TogglePerst (void) |
static PCIeInitStatus | PollForLinkUp (uint8_t pcie_inst) |
PCIeInitStatus | PCIeInit (uint8_t pcie_inst, const FwTable_PciPropertyTable *pci_prop_table) |
static int | pcie_init (void) |
SYS_INIT_APP (pcie_init) |
Variables | |
static const struct device *const | fwtable_dev = DEVICE_DT_GET(DT_NODELABEL(fwtable)) |
static const struct device * | gpio3 = DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpio3)) |
#define CMN_A_REG_MAP_BASE_ADDR 0xFFFFFFFFE1000000LL |
#define DBI_ADDR ((uint64_t)DBI_PCIE_TLB_ID << 58) |
#define DBI_PCIE_TLB_ID 62 |
#define PCIE_NOC_TLB_DATA_REG_OFFSET | ( | ID | ) |
#define PCIE_NOC_TLB_DATA_REG_OFFSET2 | ( | ID | ) |
#define PCIE_SERDES0_ALPHACORE_TLB 0 |
#define PCIE_SERDES0_CTRL_TLB 2 |
#define PCIE_SERDES1_ALPHACORE_TLB 1 |
#define PCIE_SERDES1_CTRL_TLB 3 |
#define PCIE_SERDES_SOC_REG_OFFSET 0x03000000 |
#define PCIE_SII_A_APP_PCIE_CTL_REG_OFFSET 0x0000005C |
#define PCIE_SII_A_LTSSM_STATE_REG_OFFSET 0x00000128 |
#define PCIE_SII_A_NOC_TLB_DATA_0__REG_OFFSET 0x00000134 |
#define PCIE_SII_A_NOC_TLB_DATA_62__REG_OFFSET 0x0000022C |
#define PCIE_SII_A_REG_MAP_BASE_ADDR 0xFFFFFFFFF0000000LL |
#define PCIE_SII_APP_PCIE_CTL_REG_DEFAULT (0x00000000) |
#define PCIE_SII_LTSSM_STATE_REG_DEFAULT (0x00000000) |
#define PCIE_SII_NOC_TLB_DATA_REG_DEFAULT (0x00000000) |
#define PCIE_SII_REG_TLB 4 |
#define PCIE_TLB_CONFIG_ADDR 0x1FC00000 |
#define PCIE_TLB_CONFIG_TLB 5 |
#define SERDES_INST_OFFSET 0x04000000 |
#define SERDES_SS_0_A_REG_MAP_BASE_ADDR 0xFFFFFFFFE0000000LL |
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PCIeInitStatus PCIeInit | ( | uint8_t | pcie_inst, |
const FwTable_PciPropertyTable * | pci_prop_table ) |
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SYS_INIT_APP | ( | pcie_init | ) |
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