ttnn.typecast

This table is a trace for ttnn.typecast op. Traces are generated from nightly tt-torch runs. To see nightly runs: Nightly Runs

NameInput ShapesInput LayoutsAttributesOutput ShapesOutput LayoutsPCCATOL
ttnn.typecasttensor<[16,si32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[16,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[16,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 32 + d1 * 32 + d2, d3), memory_config: (16, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[16,1,1,1,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 32 + d1 * 32 + d2, d3), memory_config: (16, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[16,250,250,1,ui32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 64000 + d1 * 256 + d2, d3), memory_config: (32000, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[16,250,250,1,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 64000 + d1 * 256 + d2, d3), memory_config: (32000, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[250,si32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 8, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[250,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 8, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,250,1,1,ui32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 8000 + d1 * 32 + d2, d3), memory_config: (250, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,250,1,1,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 8000 + d1 * 32 + d2, d3), memory_config: (250, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[16,250,250,si32]>mapping_from: (d0, d1, d2), mapping_to: (d0 * 256 + d1, d2), memory_config: (128, 8, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[16,250,250,ui32]>mapping_from: (d0, d1, d2), mapping_to: (d0 * 256 + d1, d2), memory_config: (128, 8, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[16,250,250,1,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 64000 + d1 * 256 + d2, d3), memory_config: (32000, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[16,250,250,1,bf16]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 64000 + d1 * 256 + d2, d3), memory_config: (32000, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[16,250,250,1,ui32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 64000 + d1 * 256 + d2, d3), memory_config: (32000, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[16,250,250,1,bf16]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 64000 + d1 * 256 + d2, d3), memory_config: (32000, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[16,250,250,3,bf16]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 64000 + d1 * 256 + d2, d3), memory_config: (32000, 1, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[16,250,250,3,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 64000 + d1 * 256 + d2, d3), memory_config: (32000, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[16,250,250,3,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 64000 + d1 * 256 + d2, d3), memory_config: (32000, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[16,250,250,3,f32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 64000 + d1 * 256 + d2, d3), memory_config: (32000, 1, 'tile<32x32, f32>', 'dram')nannan
ttnn.typecasttensor<[1000000,f32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 31250, 'tile<32x32, f32>', 'dram')dtype: #tt.supportedDataTypestensor<[1000000,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 31250, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[2048000,1,f32]>mapping_from: (d0, d1), mapping_to: (d0, d1), memory_config: (64000, 1, 'tile<32x32, f32>', 'dram')dtype: #tt.supportedDataTypestensor<[2048000,1,bf16]>mapping_from: (d0, d1), mapping_to: (d0, d1), memory_config: (64000, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[1000000,1,bf16]>mapping_from: (d0, d1), mapping_to: (d0, d1), memory_config: (31250, 1, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[1000000,1,f32]>mapping_from: (d0, d1), mapping_to: (d0, d1), memory_config: (31250, 1, 'tile<32x32, f32>', 'dram')nannan
ttnn.typecasttensor<[1,si32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 32 + d1 * 32 + d2, d3), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,1,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 32 + d1 * 32 + d2, d3), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,2640,768,1,ui32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 2027520 + d1 * 768 + d2, d3), memory_config: (63360, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,2640,768,1,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 2027520 + d1 * 768 + d2, d3), memory_config: (63360, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,2640,768,si32]>mapping_from: (d0, d1, d2), mapping_to: (d0 * 2656 + d1, d2), memory_config: (83, 24, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,2640,768,ui32]>mapping_from: (d0, d1, d2), mapping_to: (d0 * 2656 + d1, d2), memory_config: (83, 24, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[768,si32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 24, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[768,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 24, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,1,768,1,ui32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 768 + d1 * 768 + d2, d3), memory_config: (24, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,768,1,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 768 + d1 * 768 + d2, d3), memory_config: (24, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,2640,768,1,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 2027520 + d1 * 768 + d2, d3), memory_config: (63360, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,2640,768,1,bf16]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 2027520 + d1 * 768 + d2, d3), memory_config: (63360, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[1,2640,768,1,ui32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 2027520 + d1 * 768 + d2, d3), memory_config: (63360, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,2640,768,1,bf16]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 2027520 + d1 * 768 + d2, d3), memory_config: (63360, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[1,2640,768,3,bf16]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 2027520 + d1 * 768 + d2, d3), memory_config: (63360, 1, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[1,2640,768,3,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 2027520 + d1 * 768 + d2, d3), memory_config: (63360, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,2640,768,3,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 2027520 + d1 * 768 + d2, d3), memory_config: (63360, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,2640,768,3,f32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 2027520 + d1 * 768 + d2, d3), memory_config: (63360, 1, 'tile<32x32, f32>', 'dram')nannan
ttnn.typecasttensor<[2027520,f32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 63360, 'tile<32x32, f32>', 'dram')dtype: #tt.supportedDataTypestensor<[2027520,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 63360, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[168960,1,f32]>mapping_from: (d0, d1), mapping_to: (d0, d1), memory_config: (5280, 1, 'tile<32x32, f32>', 'dram')dtype: #tt.supportedDataTypestensor<[168960,1,bf16]>mapping_from: (d0, d1), mapping_to: (d0, d1), memory_config: (5280, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[2027520,1,bf16]>mapping_from: (d0, d1), mapping_to: (d0, d1), memory_config: (63360, 1, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[2027520,1,f32]>mapping_from: (d0, d1), mapping_to: (d0, d1), memory_config: (63360, 1, 'tile<32x32, f32>', 'dram')nannan
ttnn.typecasttensor<[1,si32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 32 + d1 * 32 + d2, d3), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,1,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 32 + d1 * 32 + d2, d3), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,300,4,1,ui32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 9600 + d1 * 32 + d2, d3), memory_config: (300, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,300,4,1,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 9600 + d1 * 32 + d2, d3), memory_config: (300, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,300,4,si32]>mapping_from: (d0, d1, d2), mapping_to: (d0 * 320 + d1, d2), memory_config: (10, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,300,4,ui32]>mapping_from: (d0, d1, d2), mapping_to: (d0 * 320 + d1, d2), memory_config: (10, 1, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[4,si32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[4,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,1,4,1,ui32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 32 + d1 * 32 + d2, d3), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,4,1,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 32 + d1 * 32 + d2, d3), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,300,4,1,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 9600 + d1 * 32 + d2, d3), memory_config: (300, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,300,4,1,bf16]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 9600 + d1 * 32 + d2, d3), memory_config: (300, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[1,300,4,1,ui32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 9600 + d1 * 32 + d2, d3), memory_config: (300, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,300,4,1,bf16]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 9600 + d1 * 32 + d2, d3), memory_config: (300, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[1,300,4,3,bf16]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 9600 + d1 * 32 + d2, d3), memory_config: (300, 1, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[1,300,4,3,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 9600 + d1 * 32 + d2, d3), memory_config: (300, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,300,4,3,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 9600 + d1 * 32 + d2, d3), memory_config: (300, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,300,4,3,f32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 9600 + d1 * 32 + d2, d3), memory_config: (300, 1, 'tile<32x32, f32>', 'dram')nannan
ttnn.typecasttensor<[1200,f32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 38, 'tile<32x32, f32>', 'dram')dtype: #tt.supportedDataTypestensor<[1200,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 38, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[33600,1,f32]>mapping_from: (d0, d1), mapping_to: (d0, d1), memory_config: (1050, 1, 'tile<32x32, f32>', 'dram')dtype: #tt.supportedDataTypestensor<[33600,1,bf16]>mapping_from: (d0, d1), mapping_to: (d0, d1), memory_config: (1050, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[1200,1,bf16]>mapping_from: (d0, d1), mapping_to: (d0, d1), memory_config: (38, 1, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[1200,1,f32]>mapping_from: (d0, d1), mapping_to: (d0, d1), memory_config: (38, 1, 'tile<32x32, f32>', 'dram')nannan
ttnn.typecasttensor<[1,si32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 32 + d1 * 32 + d2, d3), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,1,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 32 + d1 * 32 + d2, d3), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,300,80,1,ui32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 28800 + d1 * 96 + d2, d3), memory_config: (900, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,300,80,1,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 28800 + d1 * 96 + d2, d3), memory_config: (900, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,300,80,si32]>mapping_from: (d0, d1, d2), mapping_to: (d0 * 320 + d1, d2), memory_config: (10, 3, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,300,80,ui32]>mapping_from: (d0, d1, d2), mapping_to: (d0 * 320 + d1, d2), memory_config: (10, 3, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[80,si32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 3, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[80,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 3, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,1,80,1,ui32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 96 + d1 * 96 + d2, d3), memory_config: (3, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,80,1,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 96 + d1 * 96 + d2, d3), memory_config: (3, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,300,80,1,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 28800 + d1 * 96 + d2, d3), memory_config: (900, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,300,80,1,bf16]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 28800 + d1 * 96 + d2, d3), memory_config: (900, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[1,300,80,1,ui32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 28800 + d1 * 96 + d2, d3), memory_config: (900, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,300,80,1,bf16]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 28800 + d1 * 96 + d2, d3), memory_config: (900, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[1,300,80,3,bf16]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 28800 + d1 * 96 + d2, d3), memory_config: (900, 1, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[1,300,80,3,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 28800 + d1 * 96 + d2, d3), memory_config: (900, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,300,80,3,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 28800 + d1 * 96 + d2, d3), memory_config: (900, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,300,80,3,f32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 28800 + d1 * 96 + d2, d3), memory_config: (900, 1, 'tile<32x32, f32>', 'dram')nannan
ttnn.typecasttensor<[24000,f32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 750, 'tile<32x32, f32>', 'dram')dtype: #tt.supportedDataTypestensor<[24000,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 750, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[672000,1,f32]>mapping_from: (d0, d1), mapping_to: (d0, d1), memory_config: (21000, 1, 'tile<32x32, f32>', 'dram')dtype: #tt.supportedDataTypestensor<[672000,1,bf16]>mapping_from: (d0, d1), mapping_to: (d0, d1), memory_config: (21000, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[24000,1,bf16]>mapping_from: (d0, d1), mapping_to: (d0, d1), memory_config: (750, 1, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[24000,1,f32]>mapping_from: (d0, d1), mapping_to: (d0, d1), memory_config: (750, 1, 'tile<32x32, f32>', 'dram')nannan
ttnn.typecasttensor<[6,si32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[6,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,1,6,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 192 + d1 * 192 + d2 * 32 + d3, d4), memory_config: (6, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,6,1,1,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 192 + d1 * 192 + d2 * 32 + d3, d4), memory_config: (6, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[1,1,6,1,1,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 192 + d1 * 192 + d2 * 32 + d3, d4), memory_config: (6, 1, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,6,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 192 + d1 * 192 + d2 * 32 + d3, d4), memory_config: (6, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,1,6,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 192 + d1 * 192 + d2 * 32 + d3, d4), memory_config: (6, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,6,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 192 + d1 * 192 + d2 * 32 + d3, d4), memory_config: (6, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[16,si32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[16,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,16,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 512 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (16, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,16,1,1,1,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 512 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (16, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[1,16,1,1,1,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 512 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (16, 1, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[1,16,1,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 512 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (16, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,16,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 512 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (16, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,16,1,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 512 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (16, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,si32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,1,1,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (1, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,1,1,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (1, 1, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,16,6,192,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 18432 + d1 * 1152 + d2 * 192 + d3, d4), memory_config: (576, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,16,6,192,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 18432 + d1 * 1152 + d2 * 192 + d3, d4), memory_config: (576, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[192,si32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 6, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[192,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 6, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,192,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 192 + d1 * 192 + d2 * 192 + d3, d4), memory_config: (6, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,192,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 192 + d1 * 192 + d2 * 192 + d3, d4), memory_config: (6, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,16,6,192,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 18432 + d1 * 1152 + d2 * 192 + d3, d4), memory_config: (576, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,16,6,192,1,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 18432 + d1 * 1152 + d2 * 192 + d3, d4), memory_config: (576, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[1,16,6,192,4,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 18432 + d1 * 1152 + d2 * 192 + d3, d4), memory_config: (576, 1, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[1,16,6,192,4,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 18432 + d1 * 1152 + d2 * 192 + d3, d4), memory_config: (576, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecastnannan
ttnn.typecasttensor<[6,si32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[6,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,1,6,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 192 + d1 * 192 + d2 * 32 + d3, d4), memory_config: (6, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,6,1,1,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 192 + d1 * 192 + d2 * 32 + d3, d4), memory_config: (6, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[1,1,6,1,1,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 192 + d1 * 192 + d2 * 32 + d3, d4), memory_config: (6, 1, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,6,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 192 + d1 * 192 + d2 * 32 + d3, d4), memory_config: (6, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,1,6,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 192 + d1 * 192 + d2 * 32 + d3, d4), memory_config: (6, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,6,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 192 + d1 * 192 + d2 * 32 + d3, d4), memory_config: (6, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[16,si32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[16,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,16,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 512 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (16, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,16,1,1,1,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 512 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (16, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[1,16,1,1,1,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 512 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (16, 1, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[1,16,1,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 512 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (16, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,16,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 512 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (16, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,16,1,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 512 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (16, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,si32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,1,1,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (1, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,1,1,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (1, 1, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,16,6,192,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 18432 + d1 * 1152 + d2 * 192 + d3, d4), memory_config: (576, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,16,6,192,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 18432 + d1 * 1152 + d2 * 192 + d3, d4), memory_config: (576, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[192,si32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 6, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[192,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 6, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,192,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 192 + d1 * 192 + d2 * 192 + d3, d4), memory_config: (6, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,192,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 192 + d1 * 192 + d2 * 192 + d3, d4), memory_config: (6, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,16,6,192,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 18432 + d1 * 1152 + d2 * 192 + d3, d4), memory_config: (576, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,16,6,192,1,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 18432 + d1 * 1152 + d2 * 192 + d3, d4), memory_config: (576, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[1,16,6,192,4,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 18432 + d1 * 1152 + d2 * 192 + d3, d4), memory_config: (576, 1, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[1,16,6,192,4,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 18432 + d1 * 1152 + d2 * 192 + d3, d4), memory_config: (576, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecastnannan
ttnn.typecasttensor<[3,si32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[3,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,1,3,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4, d5, d6), mapping_to: (d0 * 96 + d1 * 96 + d2 * 96 + d3 * 96 + d4 * 32 + d5, d6), memory_config: (3, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,1,3,1,1,bf16]>mapping_from: (d0, d1, d2, d3, d4, d5, d6), mapping_to: (d0 * 96 + d1 * 96 + d2 * 96 + d3 * 96 + d4 * 32 + d5, d6), memory_config: (3, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,1,3,1,1,bf16]>mapping_from: (d0, d1, d2, d3, d4, d5, d6), mapping_to: (d0 * 96 + d1 * 96 + d2 * 96 + d3 * 96 + d4 * 32 + d5, d6), memory_config: (3, 1, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,1,3,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4, d5, d6), mapping_to: (d0 * 96 + d1 * 96 + d2 * 96 + d3 * 96 + d4 * 32 + d5, d6), memory_config: (3, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,1,3,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4, d5, d6), mapping_to: (d0 * 96 + d1 * 96 + d2 * 96 + d3 * 96 + d4 * 32 + d5, d6), memory_config: (3, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,1,3,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4, d5, d6), mapping_to: (d0 * 96 + d1 * 96 + d2 * 96 + d3 * 96 + d4 * 32 + d5, d6), memory_config: (3, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,si32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,1,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4, d5, d6), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3 * 32 + d4 * 32 + d5, d6), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,1,1,1,1,bf16]>mapping_from: (d0, d1, d2, d3, d4, d5, d6), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3 * 32 + d4 * 32 + d5, d6), memory_config: (1, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,1,1,1,1,bf16]>mapping_from: (d0, d1, d2, d3, d4, d5, d6), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3 * 32 + d4 * 32 + d5, d6), memory_config: (1, 1, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,1,1,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4, d5, d6), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3 * 32 + d4 * 32 + d5, d6), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,1,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4, d5, d6), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3 * 32 + d4 * 32 + d5, d6), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,1,1,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4, d5, d6), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3 * 32 + d4 * 32 + d5, d6), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,1,3,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4, d5, d6), mapping_to: (d0 * 96 + d1 * 96 + d2 * 96 + d3 * 96 + d4 * 32 + d5, d6), memory_config: (3, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,1,3,1,1,bf16]>mapping_from: (d0, d1, d2, d3, d4, d5, d6), mapping_to: (d0 * 96 + d1 * 96 + d2 * 96 + d3 * 96 + d4 * 32 + d5, d6), memory_config: (3, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,1,3,1,6,bf16]>mapping_from: (d0, d1, d2, d3, d4, d5, d6), mapping_to: (d0 * 96 + d1 * 96 + d2 * 96 + d3 * 96 + d4 * 32 + d5, d6), memory_config: (3, 1, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,1,3,1,6,si32]>mapping_from: (d0, d1, d2, d3, d4, d5, d6), mapping_to: (d0 * 96 + d1 * 96 + d2 * 96 + d3 * 96 + d4 * 32 + d5, d6), memory_config: (3, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,1,3,1,6,si32]>mapping_from: (d0, d1, d2, d3, d4, d5, d6), mapping_to: (d0 * 96 + d1 * 96 + d2 * 96 + d3 * 96 + d4 * 32 + d5, d6), memory_config: (3, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,1,3,1,6,f32]>mapping_from: (d0, d1, d2, d3, d4, d5, d6), mapping_to: (d0 * 96 + d1 * 96 + d2 * 96 + d3 * 96 + d4 * 32 + d5, d6), memory_config: (3, 1, 'tile<32x32, f32>', 'dram')nannan
ttnn.typecasttensor<[3,f32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, f32>', 'dram')dtype: #tt.supportedDataTypestensor<[3,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[12,1,f32]>mapping_from: (d0, d1), mapping_to: (d0, d1), memory_config: (1, 1, 'tile<32x32, f32>', 'dram')dtype: #tt.supportedDataTypestensor<[12,1,bf16]>mapping_from: (d0, d1), mapping_to: (d0, d1), memory_config: (1, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[3,1,bf16]>mapping_from: (d0, d1), mapping_to: (d0, d1), memory_config: (1, 1, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[3,1,f32]>mapping_from: (d0, d1), mapping_to: (d0, d1), memory_config: (1, 1, 'tile<32x32, f32>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,1,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 32 + d1 * 32 + d2, d3), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 32 + d1 * 32 + d2, d3), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,256,7,25281,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 45359104 + d1 * 177184 + d2 * 25312 + d3, d4), memory_config: (1417472, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,256,7,25281,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 45359104 + d1 * 177184 + d2 * 25312 + d3, d4), memory_config: (1417472, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,256,1,1,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 8192 + d1 * 32 + d2, d3), memory_config: (256, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,256,1,1,ui32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 8192 + d1 * 32 + d2, d3), memory_config: (256, 1, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,256,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 8192 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (256, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,256,1,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 8192 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (256, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,256,7,25281,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 8192 + d1 * 32 + d2, d3), memory_config: (256, 791, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,256,7,25281,ui32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 8192 + d1 * 32 + d2, d3), memory_config: (256, 791, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,256,7,25281,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 45359104 + d1 * 177184 + d2 * 25312 + d3, d4), memory_config: (1417472, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,256,7,25281,1,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 45359104 + d1 * 177184 + d2 * 25312 + d3, d4), memory_config: (1417472, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[1,256,7,25281,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 45359104 + d1 * 177184 + d2 * 25312 + d3, d4), memory_config: (1417472, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,256,7,25281,1,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 45359104 + d1 * 177184 + d2 * 25312 + d3, d4), memory_config: (1417472, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[1,256,7,25281,4,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 45359104 + d1 * 177184 + d2 * 25312 + d3, d4), memory_config: (1417472, 1, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[1,256,7,25281,4,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 45359104 + d1 * 177184 + d2 * 25312 + d3, d4), memory_config: (1417472, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,256,7,25281,4,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 45359104 + d1 * 177184 + d2 * 25312 + d3, d4), memory_config: (1417472, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,256,7,25281,4,f32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 45359104 + d1 * 177184 + d2 * 25312 + d3, d4), memory_config: (1417472, 1, 'tile<32x32, f32>', 'dram')nannan
ttnn.typecasttensor<[45303552,f32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1415736, 'tile<32x32, f32>', 'dram')dtype: #tt.supportedDataTypestensor<[45303552,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1415736, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[50176,1,f32]>mapping_from: (d0, d1), mapping_to: (d0, d1), memory_config: (1568, 1, 'tile<32x32, f32>', 'dram')dtype: #tt.supportedDataTypestensor<[50176,1,bf16]>mapping_from: (d0, d1), mapping_to: (d0, d1), memory_config: (1568, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[45303552,1,bf16]>mapping_from: (d0, d1), mapping_to: (d0, d1), memory_config: (1415736, 1, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[45303552,1,f32]>mapping_from: (d0, d1), mapping_to: (d0, d1), memory_config: (1415736, 1, 'tile<32x32, f32>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,1,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 32 + d1 * 32 + d2, d3), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 32 + d1 * 32 + d2, d3), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,256,7,25281,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 45359104 + d1 * 177184 + d2 * 25312 + d3, d4), memory_config: (1417472, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,256,7,25281,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 45359104 + d1 * 177184 + d2 * 25312 + d3, d4), memory_config: (1417472, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,256,1,1,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 8192 + d1 * 32 + d2, d3), memory_config: (256, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,256,1,1,ui32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 8192 + d1 * 32 + d2, d3), memory_config: (256, 1, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,256,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 8192 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (256, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,256,1,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 8192 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (256, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,256,7,25281,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 8192 + d1 * 32 + d2, d3), memory_config: (256, 791, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,256,7,25281,ui32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 8192 + d1 * 32 + d2, d3), memory_config: (256, 791, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,256,7,25281,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 45359104 + d1 * 177184 + d2 * 25312 + d3, d4), memory_config: (1417472, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,256,7,25281,1,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 45359104 + d1 * 177184 + d2 * 25312 + d3, d4), memory_config: (1417472, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[1,256,7,25281,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 45359104 + d1 * 177184 + d2 * 25312 + d3, d4), memory_config: (1417472, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,256,7,25281,1,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 45359104 + d1 * 177184 + d2 * 25312 + d3, d4), memory_config: (1417472, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[1,256,7,25281,4,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 45359104 + d1 * 177184 + d2 * 25312 + d3, d4), memory_config: (1417472, 1, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[1,256,7,25281,4,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 45359104 + d1 * 177184 + d2 * 25312 + d3, d4), memory_config: (1417472, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,256,7,25281,4,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 45359104 + d1 * 177184 + d2 * 25312 + d3, d4), memory_config: (1417472, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,256,7,25281,4,f32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 45359104 + d1 * 177184 + d2 * 25312 + d3, d4), memory_config: (1417472, 1, 'tile<32x32, f32>', 'dram')nannan
ttnn.typecasttensor<[45303552,f32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1415736, 'tile<32x32, f32>', 'dram')dtype: #tt.supportedDataTypestensor<[45303552,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1415736, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[200704,1,f32]>mapping_from: (d0, d1), mapping_to: (d0, d1), memory_config: (6272, 1, 'tile<32x32, f32>', 'dram')dtype: #tt.supportedDataTypestensor<[200704,1,bf16]>mapping_from: (d0, d1), mapping_to: (d0, d1), memory_config: (6272, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[45303552,1,bf16]>mapping_from: (d0, d1), mapping_to: (d0, d1), memory_config: (1415736, 1, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[45303552,1,f32]>mapping_from: (d0, d1), mapping_to: (d0, d1), memory_config: (1415736, 1, 'tile<32x32, f32>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,1,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 32 + d1 * 32 + d2, d3), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 32 + d1 * 32 + d2, d3), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,256,7,25281,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 45359104 + d1 * 177184 + d2 * 25312 + d3, d4), memory_config: (1417472, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,256,7,25281,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 45359104 + d1 * 177184 + d2 * 25312 + d3, d4), memory_config: (1417472, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,256,1,1,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 8192 + d1 * 32 + d2, d3), memory_config: (256, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,256,1,1,ui32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 8192 + d1 * 32 + d2, d3), memory_config: (256, 1, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,256,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 8192 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (256, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,256,1,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 8192 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (256, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,256,7,25281,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 8192 + d1 * 32 + d2, d3), memory_config: (256, 791, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,256,7,25281,ui32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 8192 + d1 * 32 + d2, d3), memory_config: (256, 791, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,256,7,25281,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 45359104 + d1 * 177184 + d2 * 25312 + d3, d4), memory_config: (1417472, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,256,7,25281,1,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 45359104 + d1 * 177184 + d2 * 25312 + d3, d4), memory_config: (1417472, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[1,256,7,25281,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 45359104 + d1 * 177184 + d2 * 25312 + d3, d4), memory_config: (1417472, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,256,7,25281,1,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 45359104 + d1 * 177184 + d2 * 25312 + d3, d4), memory_config: (1417472, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[1,256,7,25281,4,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 45359104 + d1 * 177184 + d2 * 25312 + d3, d4), memory_config: (1417472, 1, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[1,256,7,25281,4,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 45359104 + d1 * 177184 + d2 * 25312 + d3, d4), memory_config: (1417472, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,256,7,25281,4,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 45359104 + d1 * 177184 + d2 * 25312 + d3, d4), memory_config: (1417472, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,256,7,25281,4,f32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 45359104 + d1 * 177184 + d2 * 25312 + d3, d4), memory_config: (1417472, 1, 'tile<32x32, f32>', 'dram')nannan
ttnn.typecasttensor<[45303552,f32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1415736, 'tile<32x32, f32>', 'dram')dtype: #tt.supportedDataTypestensor<[45303552,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1415736, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[12544,1,f32]>mapping_from: (d0, d1), mapping_to: (d0, d1), memory_config: (392, 1, 'tile<32x32, f32>', 'dram')dtype: #tt.supportedDataTypestensor<[12544,1,bf16]>mapping_from: (d0, d1), mapping_to: (d0, d1), memory_config: (392, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[45303552,1,bf16]>mapping_from: (d0, d1), mapping_to: (d0, d1), memory_config: (1415736, 1, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[45303552,1,f32]>mapping_from: (d0, d1), mapping_to: (d0, d1), memory_config: (1415736, 1, 'tile<32x32, f32>', 'dram')nannan
ttnn.typecasttensor<[25281,si32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 791, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[25281,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 791, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,1,25281,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 808992 + d1 * 808992 + d2 * 32 + d3, d4), memory_config: (25281, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,25281,1,1,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 808992 + d1 * 808992 + d2 * 32 + d3, d4), memory_config: (25281, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[1,1,25281,1,1,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 808992 + d1 * 808992 + d2 * 32 + d3, d4), memory_config: (25281, 1, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,25281,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 808992 + d1 * 808992 + d2 * 32 + d3, d4), memory_config: (25281, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,1,25281,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 808992 + d1 * 808992 + d2 * 32 + d3, d4), memory_config: (25281, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,25281,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 808992 + d1 * 808992 + d2 * 32 + d3, d4), memory_config: (25281, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[7,si32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[7,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,7,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 224 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (7, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,7,1,1,1,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 224 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (7, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[1,7,1,1,1,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 224 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (7, 1, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[1,7,1,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 224 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (7, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,7,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 224 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (7, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,7,1,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 224 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (7, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,si32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,1,1,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (1, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,1,1,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (1, 1, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,7,25281,2,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 5662944 + d1 * 808992 + d2 * 32 + d3, d4), memory_config: (176967, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,7,25281,2,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 5662944 + d1 * 808992 + d2 * 32 + d3, d4), memory_config: (176967, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[2,si32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[2,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,2,1,ui32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,2,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3, d4), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,7,25281,2,1,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 5662944 + d1 * 808992 + d2 * 32 + d3, d4), memory_config: (176967, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,7,25281,2,1,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 5662944 + d1 * 808992 + d2 * 32 + d3, d4), memory_config: (176967, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[1,7,25281,2,4,bf16]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 5662944 + d1 * 808992 + d2 * 32 + d3, d4), memory_config: (176967, 1, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[1,7,25281,2,4,si32]>mapping_from: (d0, d1, d2, d3, d4), mapping_to: (d0 * 5662944 + d1 * 808992 + d2 * 32 + d3, d4), memory_config: (176967, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[160,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 5, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[160,si32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 5, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[160,si32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 5, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[160,bf16]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 5, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[160,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 5, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[160,bf16]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 5, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[160,bf16]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 5, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[160,si32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 5, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[8,si32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[8,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,8,1,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4, d5), mapping_to: (d0 * 256 + d1 * 32 + d2 * 32 + d3 * 32 + d4, d5), memory_config: (8, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,8,1,1,1,1,bf16]>mapping_from: (d0, d1, d2, d3, d4, d5), mapping_to: (d0 * 256 + d1 * 32 + d2 * 32 + d3 * 32 + d4, d5), memory_config: (8, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[1,8,1,1,1,1,bf16]>mapping_from: (d0, d1, d2, d3, d4, d5), mapping_to: (d0 * 256 + d1 * 32 + d2 * 32 + d3 * 32 + d4, d5), memory_config: (8, 1, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[1,8,1,1,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4, d5), mapping_to: (d0 * 256 + d1 * 32 + d2 * 32 + d3 * 32 + d4, d5), memory_config: (8, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,8,1,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4, d5), mapping_to: (d0 * 256 + d1 * 32 + d2 * 32 + d3 * 32 + d4, d5), memory_config: (8, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,8,1,1,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4, d5), mapping_to: (d0 * 256 + d1 * 32 + d2 * 32 + d3 * 32 + d4, d5), memory_config: (8, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,si32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4, d5), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3 * 32 + d4, d5), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,1,1,1,bf16]>mapping_from: (d0, d1, d2, d3, d4, d5), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3 * 32 + d4, d5), memory_config: (1, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,1,1,1,bf16]>mapping_from: (d0, d1, d2, d3, d4, d5), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3 * 32 + d4, d5), memory_config: (1, 1, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,1,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4, d5), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3 * 32 + d4, d5), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4, d5), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3 * 32 + d4, d5), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,1,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4, d5), mapping_to: (d0 * 32 + d1 * 32 + d2 * 32 + d3 * 32 + d4, d5), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,8,160,160,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4, d5), mapping_to: (d0 * 6553600 + d1 * 819200 + d2 * 5120 + d3 * 32 + d4, d5), memory_config: (204800, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,8,160,160,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4, d5), mapping_to: (d0 * 6553600 + d1 * 819200 + d2 * 5120 + d3 * 32 + d4, d5), memory_config: (204800, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[160,si32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 5, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[160,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 5, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,1,160,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4, d5), mapping_to: (d0 * 5120 + d1 * 5120 + d2 * 32 + d3 * 32 + d4, d5), memory_config: (160, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,160,1,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4, d5), mapping_to: (d0 * 5120 + d1 * 5120 + d2 * 32 + d3 * 32 + d4, d5), memory_config: (160, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,160,1,1,ui32]>mapping_from: (d0, d1, d2, d3, d4, d5), mapping_to: (d0 * 5120 + d1 * 5120 + d2 * 5120 + d3 * 32 + d4, d5), memory_config: (160, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,160,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4, d5), mapping_to: (d0 * 5120 + d1 * 5120 + d2 * 5120 + d3 * 32 + d4, d5), memory_config: (160, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,8,160,160,1,1,si32]>mapping_from: (d0, d1, d2, d3, d4, d5), mapping_to: (d0 * 6553600 + d1 * 819200 + d2 * 5120 + d3 * 32 + d4, d5), memory_config: (204800, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,8,160,160,1,1,bf16]>mapping_from: (d0, d1, d2, d3, d4, d5), mapping_to: (d0 * 6553600 + d1 * 819200 + d2 * 5120 + d3 * 32 + d4, d5), memory_config: (204800, 1, 'tile<32x32, bf16>', 'dram')nannan
ttnn.typecasttensor<[1,si32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,ui32]>mapping_from: (d0), mapping_to: (0, d0), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')nannan
ttnn.typecasttensor<[1,1,1,1,ui32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 32 + d1 * 32 + d2, d3), memory_config: (1, 1, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,1,1,1,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 32 + d1 * 32 + d2, d3), memory_config: (1, 1, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,256,7,25281,ui32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 8192 + d1 * 32 + d2, d3), memory_config: (256, 791, 'tile<32x32, u32>', 'dram')dtype: #tt.supportedDataTypestensor<[1,256,7,25281,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 8192 + d1 * 32 + d2, d3), memory_config: (256, 791, 'tile<32x32, si32>', 'dram')nannan
ttnn.typecasttensor<[1,256,7,25281,bf16]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 8192 + d1 * 32 + d2, d3), memory_config: (256, 791, 'tile<32x32, bf16>', 'dram')dtype: #tt.supportedDataTypestensor<[1,256,7,25281,si32]>mapping_from: (d0, d1, d2, d3), mapping_to: (d0 * 8192 + d1 * 32 + d2, d3), memory_config: (256, 791, 'tile<32x32, si32>', 'dram')nannan