SoC Integration Checklist

Use this checklist as a quick route through the integration work; each item links to its detailed requirements elsewhere in this guide. Record minimum evidence against each gate before sign-off.

1. Integration gates

Done Integration gate Minimum evidence Reference

Done	Integration gate	Minimum evidence	Reference
[ ]	Select the delivered hierarchy, enabled subsystems, and required configuration	Selected hierarchy and configuration record reviewed	SMU Top-Level Integration
[ ]	Assign the chiplet address envelope and program the SEP and SMC apertures	Approved non-overlapping address map; aperture CSRs verified in simulation	Address Map Integration
[ ]	Connect clocks, resets, power-good, and configuration straps; follow the power-up sequence	Clock/reset/power review and sequencing test pass	SMC Integration, SEP Integration
[ ]	Connect external pin, bus, memory, eFuse, peripheral, and debug interfaces	Interface connectivity and tie-off audit complete	SMC Integration, DTP Integration, SEP Integration
[ ]	Verify boot and reset progression, including fuse sensing, memory repair or bypass, ROM execution, and SEP release when enabled	Successful boot and reset log including failure paths	SMC Integration, SEP Integration
[ ]	Confirm that the system fabric meets the `smu_axi_in` boundary contract: no atomic transactions and only legal AXI4 bursts	Fabric configuration or protocol-checker evidence that `AWATOP` is 0 and every burst is legal at `smu_axi_in`	AXI boundary contract
[ ]	Drive AxPROT[1] (NS) and AxUSER[3:0] (source ID) of each `smu_axi_in` request from the requester’s security state and identity	Fabric mapping of security state and requester identity to NS and source ID reviewed; inbound filter test with non-zero `src_id`	AXI boundary contract
[ ]	Carry NS and the source ID from `smu_axi_out` into the system fabric’s security attribute and downstream filters	Fabric mapping reviewed; any override or dropped attribute recorded as a security decision	AXI boundary contract
[ ]	Apply technology-mapping and CDC constraints; run integration-level verification	Lint, CDC/RDC, constraint, and integration-test reports archived	Prim Cell Replacement, CDC Timing Constraints, SMU Integration Testbench, Why Open Chiplet Atlas Harness
[ ]	For each adopter-owned IP, select its trust and attachment class and complete the User IP integration checklist	User IP integration checklist completed per IP block	User IP integration checklist (see the User IP Integration chapter)

[ ]

Select the delivered hierarchy, enabled subsystems, and required configuration

Selected hierarchy and configuration record reviewed

SMU Top-Level Integration

[ ]

Assign the chiplet address envelope and program the SEP and SMC apertures

Approved non-overlapping address map; aperture CSRs verified in simulation

Address Map Integration

[ ]

Connect clocks, resets, power-good, and configuration straps; follow the power-up sequence

Clock/reset/power review and sequencing test pass

SMC Integration, SEP Integration

[ ]

Connect external pin, bus, memory, eFuse, peripheral, and debug interfaces

Interface connectivity and tie-off audit complete

SMC Integration, DTP Integration, SEP Integration

[ ]

Verify boot and reset progression, including fuse sensing, memory repair or bypass, ROM execution, and SEP release when enabled

Successful boot and reset log including failure paths

SMC Integration, SEP Integration

[ ]

Confirm that the system fabric meets the smu_axi_in boundary contract: no atomic transactions and only legal AXI4 bursts

Fabric configuration or protocol-checker evidence that AWATOP is 0 and every burst is legal at smu_axi_in

AXI boundary contract

[ ]

Drive AxPROT[1] (NS) and AxUSER[3:0] (source ID) of each smu_axi_in request from the requester’s security state and identity

Fabric mapping of security state and requester identity to NS and source ID reviewed; inbound filter test with non-zero src_id

AXI boundary contract

[ ]

Carry NS and the source ID from smu_axi_out into the system fabric’s security attribute and downstream filters

Fabric mapping reviewed; any override or dropped attribute recorded as a security decision

AXI boundary contract

[ ]

Apply technology-mapping and CDC constraints; run integration-level verification

Lint, CDC/RDC, constraint, and integration-test reports archived

Prim Cell Replacement, CDC Timing Constraints, SMU Integration Testbench, Why Open Chiplet Atlas Harness

[ ]

For each adopter-owned IP, select its trust and attachment class and complete the User IP integration checklist

User IP integration checklist completed per IP block

User IP integration checklist (see the User IP Integration chapter)