SoC Integration Checklist

Use this checklist as a quick route through the integration work; each item links to its detailed requirements elsewhere in this guide. Record minimum evidence against each gate before sign-off.

1. Integration gates

Done	Integration gate	Minimum evidence	Reference
[ ]	Select the delivered hierarchy, enabled subsystems, and required configuration	Selected hierarchy and configuration record reviewed	SMU Top-Level Integration
[ ]	Assign the chiplet address envelope and program the SEP and SMC apertures	Approved non-overlapping address map; aperture CSRs verified in simulation	Address Map Integration
[ ]	Connect clocks, resets, power-good, and configuration straps; follow the power-up sequence	Clock/reset/power review and sequencing test pass	SMC Integration, SEP Integration
[ ]	Connect external pin, bus, memory, eFuse, peripheral, and debug interfaces	Interface connectivity and tie-off audit complete	SMC Integration, DTP Integration, SEP Integration
[ ]	Verify boot and reset progression, including fuse sensing, memory repair or bypass, ROM execution, and SEP release when enabled	Successful boot and reset log including failure paths	SMC Integration, SEP Integration
[ ]	Apply technology-mapping and CDC constraints; run integration-level verification	Lint, CDC/RDC, constraint, and integration-test reports archived	Prim Cell Replacement, CDC Timing Constraints, Why Open Chiplet Atlas Harness
[ ]	For each adopter-owned IP, select its trust and attachment class and complete the User IP integration checklist	User IP integration checklist completed per IP block	User IP integration checklist (see the User IP Integration chapter)

Done

Integration gate

Minimum evidence

Reference

[ ]

Select the delivered hierarchy, enabled subsystems, and required configuration

Selected hierarchy and configuration record reviewed

SMU Top-Level Integration

[ ]

Assign the chiplet address envelope and program the SEP and SMC apertures

Approved non-overlapping address map; aperture CSRs verified in simulation

Address Map Integration

[ ]

Connect clocks, resets, power-good, and configuration straps; follow the power-up sequence

Clock/reset/power review and sequencing test pass

SMC Integration, SEP Integration

[ ]

Connect external pin, bus, memory, eFuse, peripheral, and debug interfaces

Interface connectivity and tie-off audit complete

SMC Integration, DTP Integration, SEP Integration

[ ]

Verify boot and reset progression, including fuse sensing, memory repair or bypass, ROM execution, and SEP release when enabled

Successful boot and reset log including failure paths

SMC Integration, SEP Integration

[ ]

Apply technology-mapping and CDC constraints; run integration-level verification

Lint, CDC/RDC, constraint, and integration-test reports archived

Prim Cell Replacement, CDC Timing Constraints, Why Open Chiplet Atlas Harness

[ ]

For each adopter-owned IP, select its trust and attachment class and complete the User IP integration checklist

User IP integration checklist completed per IP block

User IP integration checklist (see the User IP Integration chapter)