RTL Filelists

OCAH ships generated, repository-relative filelists under integration/filelists/. Run tools that consume them from the repository root.

These filelists are listed in the following table, which gives the filelist needed to synthesize or simulate each system.

The filelists for synthesis come from Bender’s synth target and carry the target’s define lines. Preserve those lines when passing the filelist to a synthesis tool; see Synthesis filelist defines.

The filelists for simulation are different for Verilator and VCS. Each is the complete filelist generated by that subsystem’s DV configuration for the named simulator, including the subsystem’s testbench top, supplemental models, and tool-selected stubs. AoU’s DV environment is maintained in its vendor folder, so it is not provided at the OCAH level.

Like the synthesis filelists, the simulation filelists carry the target’s define lines. Preserve these lines when passing the filelist to a simulator.

Regenerate all filelists with make update-integration-filelists from the repository root. Add CHECK=1 to verify that committed outputs are current.