Security Processor (SEP) Integration

The Security Processor (SEP) is the Root of Trust for the chiplet, providing a physically isolated execution environment for security-critical services such as secure boot, lifecycle control, device attestation, cryptographic acceleration, and key management. This section provides practical integration procedures for adopters integrating the SEP as part of the SMU or as a standalone out-of-context IP.

For detailed architectural documentation about the SEP internal design, refer to the dedicated documentation located in the SEP reference manual. The SEP hardware overview and interconnect fabric are described in the SEP Overview and Interconnect sections.

1. Module Overview

The module in sep.sv provides the complete SEP functionality with logic-level interfaces. Technology-specific components — SRAM, ROM, and eFuse shims — are instantiated by the adopter outside SEP, following the same vendor-neutral philosophy used for the SMC.

Separately, SEP exposes interfaces for supplementary peripherals an adopter may add on rather than substitute: an external TRNG and an additional SPI controller. These are not technology-specific — SEP contains its own entropy source and SPI host — so the interfaces exist to supplement what SEP already provides, and may be left unused.

When integrated inside the SMU, the SEP’s external interfaces are passed through the SMU boundary with a sep_ prefix.

2. Clock and Reset Requirements

The SEP requires two clock inputs. Connect clk_i to the primary system clock driving all SEP internal logic. Connect clk_wdt_i to a 200 kHz clock source for the watchdog timer; this clock must be independent of the system clock so that the WDT can detect system clock failures.

The primary reset rst_ni follows the standard active-low, asynchronous assertion / synchronous deassertion convention. The dbg_rstb_i input provides a separate reset for the EL2 CPU debug module. The wdt_rst_ni input receives the watchdog reset generated by the SMC reset unit. The SEP outputs wdt_timer_rst_req_o when the WDT triggers a reset request.

3. AXI Interfaces

The SEP connects to the system through three AXI paths. The smn_outbound_axi master interface allows SEP firmware to access system resources outside the SEP domain, such as SMC registers or external memory. The smn_inbound_axi slave interface accepts requests from system masters requiring access to SEP-managed resources. System masters must access SEP register regions with single-beat transactions. The sep_ext_to_smc_axi output provides a dedicated AXI path for SEP-to-SMC transactions, connecting to the SMC’s sep_axi_in port.

An additional AXI extension port (axi_extension_axi) enables adopters to attach custom peripherals to the SEP interconnect fabric without modifying the SEP core. When unused, tie the response input to return DECERR.

4. Memory Interfaces

All SEP memory macros are instantiated externally and connected through dedicated request/response interfaces. The sep_cpu_tcm interface provides tightly-coupled memory (ICCM and DCCM) for the VeeR EL2 CPU. The sep_sram interface connects scratch SRAM used for firmware data. The sep_boot_rom interface provides the BL0 ROM containing the first-stage bootloader.

The crypto subsystem requires additional memory interfaces. sep_crypto_pka_imem_sram and sep_crypto_pka_dmem_sram connect to the OTBN public key accelerator instruction and data memories respectively. km_rom_mem and km_sram_mem connect to the Key Manager’s dedicated ROM and SRAM macros. The KM SRAM must assert rvalid at least one cycle after the cycle in which it grants a read; a registered-read macro meets this.

abr_mem connects the Adams Bridge working SRAM. On an idle cycle (re low), ABR expects the channel’s read data to return 0 the following cycle. SEP_ABR_SRAM_LATENCY must equal the macros' native registered-read latency (default 1). Word-write channels are full-word we / re / address / data. sig_z and pk carry one-bit-per-byte wstrobe; map those to the macros' byte-write enables. SEP_ABR_MASKING_EN (default 1) selects 2-share DOM: thirteen 1R1W macros versus nine, plus a second NTT. This changes ABR internal behavior (sequencing, SCA, memory topology), not merely throughput. Give the same value to SEP and to the SRAM instances. When it is 0, do not instantiate the four masked coefficient banks; their response fields read as 0.

5. Cryptographic Subsystem Connections

The SEP includes an internal entropy source that requires a ring-oscillator sample clock connected to entropy_rosc_sample_clk_i. This clock must be asynchronous to clk_i and typically runs between 100 and 400 MHz.

5.1. External TRNG

For adopters providing an external TRNG, the ext_trng_axil AXI-Lite interface connects to the external TRNG’s control registers, while the ext_trng_axis AXI-Stream interfaces carry entropy data. The ext_trng_irq_i input is routed to the PIC.

SEP decodes the 4 kB TRNG aperture (0x1091_7000 - 0x1091_7FFF) as a single window and forwards every access on ext_trng_axil. It does not decode offsets inside that window: the endpoint is an adopter-defined IP.

The adopter must perform the intra-aperture decode. An address that owns no register must return an error response and must not alias onto a live register. When no external TRNG is connected, terminate ext_trng_axil with a DECERR slave.

The TRNG path reaches ext_trng_axil through an AXI4-to-AXI-Lite conversion (64-to-32 downsizer and burst splitter). An errored read returns the slave’s response verbatim. A single-beat write does too, so a DECERR slave answers both an errored read and an errored write with DECERR. A write the splitter breaks into more than one beat is reported as SLVERR when an earlier fragment erred and the last fragment is OKAY. An adopter whose endpoint returns DECERR for an unowned offset sees that code on a single-beat access.

6. eFuse and Lifecycle

SEP has its own eFuse bank. Instantiate a separate SHIM and physical eFuse bank; do not share the SMC’s. The SHIM contract is the eFuse Interface. On sep.sv, connect efuse_bank_ctrl_* and efuse_shim_command_*. Through the SMU those ports appear as sep_efuse_bank_ctrl_* and sep_efuse_shim_command_*. The SEP SHIM control CSRs sit at the base of sep_external; see the SHIM control address window. SEP routes a burst on its first address, so a burst that begins in that window carries its later beats to the SHIM. An address that owns no SHIM register must return SLVERR and must not alias onto a live register.

SEP senses this bank after its own reset. Watch sep_fuse_sense_done_o. On sep.sv, drive smc_fuse_sense_done_i from the SMC so firmware can see when the SMC fabric is out of reset; the SMU wires that input internally.

Lifecycle and test-mode ports on sep.sv, and what to do with them. Behaviour is in the Technical Reference Manual, not here.

  • secure_tm_req_i signals a request to enter secure test mode. SEP latches it into secure_tm_o when fuse sensing completes, or at cold-reset release if SEC_DIS is already asserted. Secure test mode forces a no-secret, no-fuse-program configuration; it is not an authorization bit. See Test Mode Entry and secure_tm and the Secure Scan Chain in the TRM. secure_tm_o is also an SMU output.

  • security_disable_o is the SEC_DIS token-match result (emergency A0 unlock). On sep.sv, route it to SMC sep_security_disable_i; the SMU does that internally. See Security Disable in the TRM.

  • lc_state_o is the differentially encoded LC_STATE shadow. lc_sigint_err_o is the decode integrity error (fail-closed). Both are SMU outputs. See Life Cycle Controller in the TRM.

  • dbg_disable_o is the typed per-path debug/test disable vector (active-high: 1 = path disabled). On sep.sv, route it to DTP dbg_disable_i; the SMU does that internally.

  • lcc_demote_state_1_o / lcc_demote_state_2_o are differentially encoded in-field debug demotion. They leave the SMU for adopter lifecycle logic and are not connected to the SMC. See in-field debug demotion in the TRM.

  • sep_fuse_dft_disable_o / smc_fuse_dft_disable_o gate DFT-inserted OTP access. Leave them open if no such path is inserted. They are SMU outputs.

OTP debug AXI-Lite (axil_sep_otp_jtag) is connected to the DTP inside the SMU; when CFG.SEP=0 the SMU instantiates an AXI-Lite error slave on that path.

7. SPI Host Interface

The SEP provides a SPI host controller through the sep_io_spi interface, supporting standard, dual and quad modes. The controller’s own interrupt leaves the module as the irq field of sep_io_spi_req_o, so no separate interrupt output is needed.

7.1. SEP SPI Host Pin Assignment

When the SMU is built with the SEP, the SMU drives the SMC SPI port (spi_*_i of smc.sv) from sep_io_spi_req_o and returns the data-pad inputs to the SEP in sep_io_spi_rsp_i.sd. The SMC places these signals on GPIO 0-10 and 54. Inside smc.sv, no register selects another SPI source for these pads.

GPIO Function SEP SPI host source

0-3

SPI.DATA[0-3]

Lane n drives sd[n] with output enable sd_oe[n]; the pad input returns as sd[n].

4-7

SPI.DATA[4-7]

Not driven. Output disabled, input disabled.

8

SPI.CS

cs_n, output enable cs_oe.

9

SPI.CLK

sck, output enable sck_oe.

10

SPI.DQS

Not driven. Output disabled, input disabled.

54

SPI DQS Loopback

Not driven. Output disabled, input disabled.

In standard mode, SPI.DATA[0] is the host output (COPI) and SPI.DATA[1] is the host input (CIPO).

The SMC holds the SPI function select of these pads on whenever the SMU has the SEP. A pad follows the SEP SPI host once it is out of cold reset and while its GPIO DATA_CTRL.lsio_disable is clear; setting lsio_disable returns the pad to register control. A pad shim outside smc.sv can also hand a pad to a second function with its CONTROL.hw2_ovrd.

On SPI.CS, SPI.CLK and SPI.DATA[0-3], the pad input is enabled only while the host does not drive that pad. The host drives a data lane only while chip select is asserted, and drives no pad until software sets its CONTROL.OUTPUT_EN. Until then SPI.CS is undriven, so its level comes from the pad pull; the GPIO pin table recommends a pull-up.

8. Bring-Up Considerations

The SEP boot sequence begins after the SMC completes fuse sensing and releases the SEP reset. The SEP BL0 ROM FW verifies the BL1 software image using non-volatile public keys before transferring control. Feature controls derived from secure boot authentication and lifecycle state govern what operations are permitted after boot.

The jtag_id_i input must be tied to an appropriate constant in the top-level integration. A rst_vec_i port exists on tb_top.sv for DV reset vector injection; it is not present on sep.sv itself and requires no integration tie-off.

9. SEP Port Interface

The SEP exposes interfaces for clocks, resets, JTAG debug, CPU control, memory macros, AXI bus connections, cryptographic subsystem, eFuse, lifecycle, SPI host, and mailbox. The following table defines all SEP top-level ports.

The generated module and port pages are in the TRM under RTL Modules Reference. This table keeps each port’s connection and tie-off default.

Table 1. SEP Port Declaration
Interface Name Type Direction Width Description Connection Default value (if applicable)

clk_i

logic

Input

1

Primary SEP clock. All SEP internal logic operates synchronously to this clock.

System clock

N/A

clk_wdt_i

logic

Input

1

200 kHz clock for watchdog timer.

Low-frequency clock source

N/A

rst_ni

logic

Input

1

Primary reset (active low). Asynchronous assertion, synchronous deassertion.

System reset

N/A

dbg_rstb_i

logic

Input

1

EL2 debugger reset (active low).

JTAG debug infrastructure

N/A

wdt_rst_ni

logic

Input

1

Watchdog timer reset from SMC (active low).

SMC reset unit

N/A

wdt_timer_rst_req_o

logic

Output

1

WDT reset request output. Triggers memory interface reset in sep_wrapper.

SEP wrapper

N/A

jtag_tck_i

logic

Input

1

JTAG test clock.

JTAG pads (via DTP STAP)

N/A

jtag_tms_i

logic

Input

1

JTAG test mode select.

JTAG pads (via DTP STAP)

N/A

jtag_tdi_i

logic

Input

1

JTAG test data in.

JTAG pads (via DTP STAP)

N/A

jtag_trst_ni

logic

Input

1

JTAG test reset (active low).

JTAG pads (via DTP STAP)

N/A

jtag_tdo_o

logic

Output

1

JTAG test data out.

JTAG pads (via DTP STAP)

N/A

jtag_tdoEn_o

logic

Output

1

JTAG test data out enable.

JTAG pads (via DTP STAP)

N/A

axil_sep_otp_jtag_req_i

sep_efuse_pkg::efuse_axil_req_t

Input

-

OTP debug AXI-Lite request from JTAG.

DTP axil_sep_otp_jtag_req_o

Tie to '0 if unused

axil_sep_otp_jtag_resp_o

sep_efuse_pkg::efuse_axil_resp_t

Output

-

OTP debug AXI-Lite response to JTAG.

DTP axil_sep_otp_jtag_resp_i

N/A

mpc_debug_halt_req_i

logic

Input

1

Async halt request from MPC.

Debug controller

Tie to '0 if unused

mpc_debug_run_req_i

logic

Input

1

Async run request from MPC.

Debug controller

Tie to '0 if unused

mpc_reset_run_req_i

logic

Input

1

Run/halt selection after reset.

Debug controller

1’b1

cpu_halt_req_i

logic

Input

1

Async halt request to CPU.

Debug controller

Tie to '0 if unused

cpu_run_req_i

logic

Input

1

Async restart request to CPU.

Debug controller

Tie to '0 if unused

test_en_i

logic

Input

1

DFT/scan test-enable. Drives clock-gater test ports and AXI cell test inputs.

Test controller

1’b0

scan_rst_ni

logic

Input

1

Scan reset (active-low). Bypasses reset synchronizers during DFT.

Test controller

1’b1

ext_boot_seq_done_i

logic

Input

1

Boot sequence completion qualified to clk_i (memory repair and shadow register override done); gates reset release. In SMU, driven from SMC-qualified logic. In standalone SEP, synchronize and qualify before this port.

SMC-qualified boot done or external synchronizer

1’b1

dmi_core_enable_i

logic

Input

1

Enables DMI accesses to the core debug module (addresses 0x00-0x4F). Tied high at SMU; TAP access is already lifecycle-gated.

Debug infrastructure

1’b1

dmi_uncore_enable_i

logic

Input

1

Enables DMI accesses to an external uncore aperture (addresses 0x50+). Unused: the core debug module AXI master already reaches the SEP fabric.

Debug infrastructure

Tie to '0 if unused

dmi_uncore_en_o

logic

Output

1

DMI uncore access enable.

Debug infrastructure

N/A

dmi_uncore_wr_en_o

logic

Output

1

DMI uncore write enable.

Debug infrastructure

N/A

dmi_uncore_addr_o

logic

Output

[6:0]

DMI uncore address.

Debug infrastructure

N/A

dmi_uncore_wdata_o

logic

Output

[31:0]

DMI uncore write data.

Debug infrastructure

N/A

dmi_uncore_rdata_i

logic

Input

[31:0]

DMI uncore read data.

Debug infrastructure

N/A

dmi_active_o

logic

Output

1

DMI active indicator.

Debug infrastructure

N/A

sep_cpu_trace_o

sep_cpu_trace_t

Output

-

CPU trace output for debug.

Trace infrastructure

N/A

lockstep_ctrl_i

sep_pkg::sep_lockstep_ctrl_t

Input

-

VeeR lockstep controls: disable corruption detection, and error-injection enable. Inert unless the core is built with RV_LOCKSTEP_ENABLE.

Chip-level RAS control

Tie to '0 if unused

lockstep_status_o

sep_pkg::sep_lockstep_status_t

Output

-

VeeR lockstep status: corruption detected. Reads 0 unless the core is built with RV_LOCKSTEP_ENABLE.

Chip-level RAS aggregation

N/A

jtag_id_i

logic

Input

[31:1]

JTAG ID value.

Configuration tie-off

N/A

timer_int_i

logic

Input

1

Timer interrupt.

Internal timer

Tie to '0 if unused

soft_int_i

logic

Input

1

Software interrupt.

Software IRQ source

Tie to '0 if unused

extintsrc_req_i

logic

Input

[NUM_EXTERNAL_IRQS-1:0]

External interrupt sources for PIC.

External IRQ sources

Tie to '0 if unused

sep_cpu_tcm_req_o

sep_cpu_tcm_req_t

Output

-

CPU tightly-coupled memory (TCM) request (ICCM + DCCM).

SRAM macros

N/A

sep_cpu_tcm_rsp_i

sep_cpu_tcm_rsp_t

Input

-

CPU TCM response.

SRAM macros

N/A

sep_sram_req_o

sep_sram_req_t

Output

-

Scratch SRAM request.

SRAM macros

N/A

sep_sram_rsp_i

sep_sram_rsp_t

Input

-

Scratch SRAM response.

SRAM macros

N/A

sep_boot_rom_req_o

sep_sram_req_t

Output

-

Boot ROM (BL0) request.

ROM macro

N/A

sep_boot_rom_rsp_i

sep_sram_rsp_t

Input

-

Boot ROM (BL0) response.

ROM macro

N/A

smn_outbound_axi_req_o

sep_system_peripherals_outbound_axi_req_t

Output

-

SMN outbound AXI request (system bus master).

SMN fabric

N/A

smn_outbound_axi_resp_i

sep_system_peripherals_outbound_axi_resp_t

Input

-

SMN outbound AXI response.

SMN fabric

N/A

smn_inbound_axi_req_i

sep_system_peripherals_internal_axi_req_t

Input

-

SMN inbound AXI request (system bus slave).

SMN fabric

Tie to '0 if unused

smn_inbound_axi_resp_o

sep_system_peripherals_internal_axi_resp_t

Output

-

SMN inbound AXI response.

SMN fabric

N/A

sep_ext_to_smc_axi_req_o

sep_system_peripherals_internal_axi_req_t

Output

-

SEP-to-SMC AXI request. Dedicated path for SEP to access SMC resources.

SMC sep_axi_in_req_i

N/A

sep_ext_to_smc_axi_resp_i

sep_system_peripherals_internal_axi_resp_t

Input

-

SEP-to-SMC AXI response.

SMC sep_axi_in_resp_o

N/A

entropy_rosc_sample_clk_i

logic

Input

1

Ring-oscillator sample clock for entropy source (async vs clk_i; ~100-400 MHz typical).

Ring oscillator

N/A

sep_crypto_pka_imem_sram_req_o

sep_crypto_pka_imem_sram_req_t

Output

-

OTBN PKA instruction memory SRAM request.

SRAM macro

N/A

sep_crypto_pka_imem_sram_rsp_i

sep_crypto_pka_imem_sram_rsp_t

Input

-

OTBN PKA instruction memory SRAM response.

SRAM macro

N/A

sep_crypto_pka_dmem_sram_req_o

sep_crypto_pka_dmem_sram_req_t

Output

-

OTBN PKA data memory SRAM request.

SRAM macro

N/A

sep_crypto_pka_dmem_sram_rsp_i

sep_crypto_pka_dmem_sram_rsp_t

Input

-

OTBN PKA data memory SRAM response.

SRAM macro

N/A

ext_trng_axil_req_o

sep_32_32_axil_req_t

Output

-

External TRNG AXI-Lite passthrough request (to sep_ip_integration).

External TRNG shim

N/A

ext_trng_axil_resp_i

sep_32_32_axil_resp_t

Input

-

External TRNG AXI-Lite passthrough response.

External TRNG shim

N/A

ext_trng_axis_req_i

ext_trng_axis_req_t

Input

[EXT_TRNG_NUM_AXIS-1:0]

External TRNG AXI-Stream request array (from sep_ip_integration).

External TRNG shim

N/A

ext_trng_axis_rsp_o

ext_trng_axis_rsp_t

Output

[EXT_TRNG_NUM_AXIS-1:0]

External TRNG AXI-Stream response array.

External TRNG shim

N/A

ext_trng_irq_i

logic

Input

1

External TRNG interrupt (routed to PIC).

External TRNG shim

Tie to '0 if unused

km_rom_mem_req_o

km_intf_pkg::km_rom_mem_req_t

Output

-

Key Manager ROM memory request.

ROM macro

N/A

km_rom_mem_rsp_i

km_intf_pkg::km_rom_mem_rsp_t

Input

-

Key Manager ROM memory response.

ROM macro

N/A

km_sram_mem_req_o

km_intf_pkg::km_sram_mem_req_t

Output

-

Key Manager SRAM memory request.

SRAM macro

N/A

km_sram_mem_rsp_i

km_intf_pkg::km_sram_mem_rsp_t

Input

-

Key Manager SRAM memory response.

SRAM macro

N/A

efuse_bank_ctrl_req_o

sep_efuse_pkg::efuse_axil_req_t

Output

-

eFuse bank control AXI-Lite request.

eFuse shim

N/A

efuse_bank_ctrl_resp_i

sep_efuse_pkg::efuse_axil_resp_t

Input

-

eFuse bank control AXI-Lite response.

eFuse shim

N/A

efuse_shim_command_req_o

sep_efuse_pkg::fuse_command_req_t

Output

-

eFuse command interface request.

eFuse shim

N/A

efuse_shim_command_resp_i

sep_efuse_pkg::fuse_command_resp_t

Input

-

eFuse command interface response.

eFuse shim

N/A

lcc_demote_state_1_o

logic

Output

[1:0]

Lifecycle demote state output 1. Exported at SMU boundary; not currently connected to SMC.

SMU external port

N/A

lcc_demote_state_2_o

logic

Output

[1:0]

Lifecycle demote state output 2. Exported at SMU boundary; not currently connected to SMC.

SMU external port

N/A

sep_io_spi_req_o

sep_io_spi_req_t

Output

-

SPI host controller request.

SPI pad interface

N/A

sep_io_spi_rsp_i

sep_io_spi_rsp_t

Input

-

SPI host controller response.

SPI pad interface

N/A

lc_state_o

logic

Output

[2*LcStateBitWidth-1:0]

Lifecycle state output (differentially encoded). Routed to SMC and the SMU external output; debug-disable control to DTP is via dbg_disable_o.

SMC, SMU external

N/A

dbg_disable_o

sep_lifecycle_ctrl_pkg::dbg_disable_t

Output

-

Typed debug-disable struct routed by SMU to DTP debug-disable control.

SMU → DTP

N/A

sep_fuse_dft_disable_o

logic

Output

1

Gate for the DFT-inserted access path into the SEP OTP, composed as Case 3 AND SEP_FUSE_DBG. Unconnected in the functional design; an adopter’s DFT insertion connects it.

Adopter DFT insertion

Leave open if no path is inserted

smc_fuse_dft_disable_o

logic

Output

1

Gate for the DFT-inserted access path into the SMC OTP, composed as Case 2 AND SMC_FUSE_DBG. Unconnected in the functional design; an adopter’s DFT insertion connects it.

Adopter DFT insertion

Leave open if no path is inserted

lc_sigint_err_o

logic

Output

1

Lifecycle signal integrity error.

SMU

N/A

security_disable_o

logic

Output

1

Security disable output.

SMU

N/A

secure_tm_o

logic

Output

1

Secure test mode output.

SMU

N/A

smc_mailbox_interrupt_o

logic

Output

[NumMailboxes-1:0]

Mailbox interrupt outputs to SMC.

SMC interrupt aggregator

N/A

smc_fuse_sense_done_i

logic

Input

1

SMC fuse sense done indication.

SMC fuse_sense_done_o

N/A

sep_fuse_sense_done_o

logic

Output

1

SEP fuse sense done output.

System integration

N/A

secure_tm_req_i

logic

Input

-

Secure test mode request.

GPIO padring / tie-off

N/A

axi_extension_axi_req_o

sep_32_64_6_12_axi_req_t

Output

-

AXI extension port request for adopter peripheral expansion.

Adopter peripherals

N/A

axi_extension_axi_resp_i

sep_32_64_6_12_axi_resp_t

Input

-

AXI extension port response.

Adopter peripherals

Tie to DECERR if unused

smc_global_base_addr_i

logic

Input

[55:0]

SMC global base address for outbound address translation.

System configuration

N/A

smc_region_size_i

logic

Input

[55:0]

SMC region size for outbound address translation.

SMC smc_region_size_o

N/A

km_unrecoverable_err_o

logic

Output

1

Key Manager unrecoverable error.

RAS / error handling

N/A

km_recoverable_err_o

logic

Output

1

Key Manager recoverable error.

RAS / error handling

N/A

ext_debug_bus_o

logic

Output

[511:0]

External debug observation bus.

Debug infrastructure

N/A