Debug & Test Ports (DTP) Integration

1. Configuration

The SMU smu_cfg_t fields XTRIG_NUM_CTP, XTRIG_NUM_INT_CT, and XTRIG_NUM_CLK_STOP_REQ size the SMU-exposed cross-trigger ports and are passed through to the DTP (with the SMC-reserved lanes added to the internal-CT and clock-stop counts). The generated Cross Trigger Matrix register map must have one CT_Src and one CT_Dst for every DTP port (XTRIG_NUM_CTP + XTRIG_NUM_INT_CT at the DTP, which is the SMU-exposed internal-CT count plus smu_pkg::XtrigSmcIntCtLanes). Resizing is two steps: set the CFG counts, and regenerate the CTM with matching PeakRDL overrides:

make ocah-regen-regs TARGET=cross_trigger_matrix \
    OCAH_REG_RDL_PARAMS_cross_trigger_matrix="NUM_CT_SRC=<n> NUM_CT_DST=<n>"

<n> is the DTP total (CFG.XTRIG_NUM_CTP + CFG.XTRIG_NUM_INT_CT smu_pkg::XtrigSmcIntCtLanes). cross_trigger_network fails elaboration if the parameterized total disagrees with the generated map. Defaults remain 16 external CTPs, 10 internal CTs (8 exposed), and 9 clock-stop requests (8 exposed). XTRIG_INT_CT_MODE and every JTAG_* enable are set at the instantiation as shown below.

Include the DTP in your build using Bender target dtp, which pulls in the DTP RTL together with the JTAG and cross-trigger IPs it instantiates. The legacy filelist hw/sys/dtp/rtl/config/dtp.f covers only the JTAG portion of the hierarchy and is not a complete DTP recipe.

2. Instantiation

dtp #(
    // JTAG Configuration
    .JTAG_BSR_ENABLE          (1'b1),
    .JTAG_TMP_ENABLE          (1'b1),
    .JTAG_SMC_DBG_ENABLE      (1'b1),
    .JTAG_SEP_DBG_ENABLE      (1'b1),
    .JTAG_IDCODE_MFR_ID       (11'h15A),
    .JTAG_IDCODE_PART_NUM     (16'h1234),
    .JTAG_IDCODE_SI_REV       (4'h1),
    // Cross Trigger Configuration
    .XTRIG_NUM_CTP            (16),
    .XTRIG_NUM_INT_CT         (10),
    .XTRIG_NUM_CLK_STOP_REQ   (9),
    .XTRIG_INT_CT_MODE        (10'b0000000000)
) u_dtp (
    .clk_i                    (clk),
    .rst_n_i                  (rst_n),
    .pwr_on_rst_ni            (pwr_on_rst_n),
    // JTAG, Boundary Scan, Cross Trigger interfaces...
);

3. Clock and Reset

TCK Domain: JTAG logic operates on external Test Clock
System Clock (clk_i): Cross trigger logic and JTAG2AXI bridges
System Reset (rst_n_i): Resets cross trigger and AXI; does not affect TAP controller
Power-On Reset (pwr_on_rst_ni): Asynchronous reset for JTAG state machine

4. Constraints

JTAG interface: 10-50 MHz TCK frequency
Cross trigger signals synchronized to system clock
DTP remains active during clock stop for debug access
External CTP signals require pad ring integration with ESD protection

5. STAP Scan Chain Topology

The DTP secondary scan path chains multiple STAPs on a single PTAP-managed scan string. The fixed order on this string is: PTAP, I/O STAP (if JTAG_STAP_IO_ENABLE=1), SMC debug STAP (if JTAG_SMC_DBG_ENABLE=1), SEP debug STAP (if CFG.SEP=1 in the SMU), extra STAP[N-1:0], and return to PTAP.

The string carries scans only while the PTAP 3DCR select bit is set. While the bit is clear, the scan-control strobes to every STAP stay low, so the STAP SIBs and 3DCRs hold their state through every PTAP scan, as does the downstream TAP of every deselected STAP. A STAP whose own select bit is set still forwards TCK and the live TMS, so its downstream TAP follows every PTAP scan; clear each STAP’s select bit, or reset the chain, before clearing the PTAP select bit. The select bit updates at Update-DR, so it is set in a TAP_3DCR scan of its own before a scan that opens STAP SIBs or writes STAP 3DCRs.

Both the SMC and SEP debug STAP host interfaces are internal to the SMU and are not exported on the SMU boundary. The SMU wires the SMC debug STAP host outputs to the SMC CPU/system JTAG ports (smc_cpu_jtag_*) when JTAG_SMC_DBG_ENABLE=1; when disabled, the DTP bypasses this STAP in the secondary scan chain and drives the internal host outputs low. The SEP debug STAP connects to the SEP JTAG debug port when CFG.SEP=1; when CFG.SEP=0, the SMU ties sep_stap_tdo_to_dtp = 1’b0 to bypass the SEP STAP return path.

Each STAP host interface is gated by a field of dbg_disable_i, synchronized to TCK inside the DTP. Each field is active-high (1 = path disabled).

STAP Disable Field

STAP	Disable Field
I/O STAP	`dbg_disable_i.stap_io`
SMC debug STAP	`dbg_disable_i.stap_smc`
SEP debug STAP	`dbg_disable_i.stap_sep`
Extra STAPs	`dbg_disable_i.stap_extra`
External STAP return path	`dbg_disable_i.stap_host`

I/O STAP

dbg_disable_i.stap_io

SMC debug STAP

dbg_disable_i.stap_smc

SEP debug STAP

dbg_disable_i.stap_sep

Extra STAPs

dbg_disable_i.stap_extra

External STAP return path

dbg_disable_i.stap_host

The full set of debug-disable-gated paths, including the iJTAG chains and the JTAG2AXI bridges, is tabulated in the DTP JTAG integration section of the TRM.

6. DTP Port Interface

The DTP exposes interfaces for JTAG TAP control, boundary scan, multiple STAP host ports, iJTAG scan chains, AXI debug bridges, cross trigger networks, and CTP GPIO pads. The following table defines all DTP top-level ports. Refer to the dedicated DTP documentation in hw/sys/dtp/doc/ for internal design details.

The generated module and port pages are in the TRM under RTL Modules Reference. This table keeps each port’s connection and tie-off default.

Legend: Where no Default entry is shown in Description / Default, the original port reference specifies N/A — those ports have no integrator-supplied default; connect as directed by Description.

DTP Port Declaration lists the DTP boundary ports, their dimensions, and their connections.

Table 1. DTP Port Declaration
Interface Name	Type	Dir	Width	Description / Default	Connection
`clk_i`	`logic`	In	1	System clock for cross trigger logic and JTAG2AXI bridges.	System clock
`rst_n_i`	`logic`	In	1	System reset (active low). Resets cross trigger and AXI logic; does not affect the TAP controller.	System reset
`pwr_on_rst_ni`	`logic`	In	1	Power-on reset for JTAG state machine (active low, asynchronous).	Power-on reset
`dbg_disable_i`	`sep_lifecycle_ctrl_pkg::dbg_disable_t`	In	-	Per-path lifecycle controls for disabling debug and test interfaces. Active-high (1 = path disabled). DTP synchronizes each field into the JTAG TCK domain.	SEP lifecycle controller or adopter-equivalent policy source
`jtag_ptap_client_tap_ctrl_i`	`jtag_tap_ctrl_t`	In	-	Primary JTAG TAP control (TCK, TMS, TRST_N).	External JTAG pads
`jtag_ptap_client_tdi_i`	`logic`	In	1	Primary JTAG TDI.	External JTAG pads
`jtag_ptap_client_tdo_o`	`logic`	Out	1	Primary JTAG TDO.	External JTAG pads
`jtag_ptap_client_tdo_oen_o`	`logic`	Out	1	Primary JTAG TDO output enable.	External JTAG pads
`jtag_bsr_host_scan_ctrl_o`	`jtag_scan_ctrl_t`	Out	-	Boundary scan control. Tie scan_in to scan_out if BSR is disabled.	Boundary scan chain
`jtag_bsr_host_scan_in_i`	`logic`	In	1	Boundary scan data in.	Boundary scan chain
`jtag_bsr_host_scan_out_o`	`logic`	Out	1	Boundary scan data out.	Boundary scan chain
`jtag_stap_io_host_tap_ctrl_o`	`jtag_tap_ctrl_t`	Out	-	I/O STAP TAP control for chiplet-to-chiplet connectivity. If `JTAG_STAP_IO_ENABLE=0`, only `.tck` is driven; `.tms` is 0 and `.trst_n` is 0, so TRST is asserted and a TAP connected to the port is held in Test-Logic-Reset.	I/O STAP host
`jtag_stap_io_host_tdi_i`	`logic`	In	1	I/O STAP TDI. Default: Tie to '0 if unused.	I/O STAP host
`jtag_stap_io_host_tdo_o`	`logic`	Out	1	I/O STAP TDO.	I/O STAP host
`jtag_stap_io_host_tdo_oen_o`	`logic`	Out	1	I/O STAP TDO output enable.	I/O STAP host
`jtag_stap_smc_host_tap_ctrl_o`	`jtag_tap_ctrl_t`	Out	-	SMC debug STAP TAP control. If `JTAG_SMC_DBG_ENABLE=0`, only `.tck` is driven; `.tms` is 0 and `.trst_n` is 0, so TRST is asserted and a TAP connected to the port is held in Test-Logic-Reset.	SMC JTAG port
`jtag_stap_smc_host_tdi_i`	`logic`	In	1	SMC debug STAP TDI (from SMC TDO). Default: Tie to '0 if unused.	SMC JTAG port
`jtag_stap_smc_host_tdo_o`	`logic`	Out	1	SMC debug STAP TDO (to SMC TDI).	SMC JTAG port
`jtag_stap_smc_host_tdo_oen_o`	`logic`	Out	1	SMC debug STAP TDO output enable.	SMC JTAG port
`jtag_stap_sep_host_tap_ctrl_o`	`jtag_tap_ctrl_t`	Out	-	SEP debug STAP TAP control. If `JTAG_SEP_DBG_ENABLE=0`, only `.tck` is driven; `.tms` is 0 and `.trst_n` is 0, so TRST is asserted and a TAP connected to the port is held in Test-Logic-Reset.	SEP JTAG port
`jtag_stap_sep_host_tdi_i`	`logic`	In	1	SEP debug STAP TDI (from SEP TDO). Default: Tie to '0 if unused.	SEP JTAG port
`jtag_stap_sep_host_tdo_o`	`logic`	Out	1	SEP debug STAP TDO (to SEP TDI).	SEP JTAG port
`jtag_stap_sep_host_tdo_oen_o`	`logic`	Out	1	SEP debug STAP TDO output enable.	SEP JTAG port
`jtag_stap_extra_host_tap_ctrl_o`	`jtag_tap_ctrl_t`	Out	`[JtagNumExtraStapPorts-1:0]`	Extra STAP TAP control array. If `JTAG_NUM_EXTRA_STAPS=0`, the single padded element drives only `.tck`; its `.tms` is 0 and its `.trst_n` is 0, so TRST is asserted and a TAP connected to it is held in Test-Logic-Reset.	Extra STAP hosts
`jtag_stap_extra_host_tdi_i`	`logic`	In	`[JtagNumExtraStapPorts-1:0]`	Extra STAP TDI array. Default: Tie to '0 if unused.	Extra STAP hosts
`jtag_stap_extra_host_tdo_o`	`logic`	Out	`[JtagNumExtraStapPorts-1:0]`	Extra STAP TDO array.	Extra STAP hosts
`jtag_stap_extra_host_tdo_oen_o`	`logic`	Out	`[JtagNumExtraStapPorts-1:0]`	Extra STAP TDO output enable array.	Extra STAP hosts
`jtag_stap_host_scan_ctrl_o`	`jtag_scan_ctrl_t`	Out	-	Extended STAP scan control. Tie scan_in to scan_out if unused.	STAP scan chain
`jtag_stap_host_scan_in_i`	`logic`	In	1	Extended STAP scan data in.	STAP scan chain
`jtag_stap_host_scan_out_o`	`logic`	Out	1	Extended STAP scan data out.	STAP scan chain
`jtag_dfd_host_scan_ctrl_o`	`jtag_scan_ctrl_t`	Out	-	DFD iJTAG scan control. Tie scan_in to scan_out if unused.	DFD iJTAG chain
`jtag_dfd_host_scan_in_i`	`logic`	In	1	DFD iJTAG scan data in.	DFD iJTAG chain
`jtag_dfd_host_scan_out_o`	`logic`	Out	1	DFD iJTAG scan data out.	DFD iJTAG chain
`jtag_dft_secure_host_scan_ctrl_o`	`jtag_scan_ctrl_t`	Out	-	Secure DFT iJTAG scan control. Tie scan_in to scan_out if unused.	Secure DFT iJTAG chain
`jtag_dft_secure_host_scan_in_i`	`logic`	In	1	Secure DFT iJTAG scan data in.	Secure DFT iJTAG chain
`jtag_dft_secure_host_scan_out_o`	`logic`	Out	1	Secure DFT iJTAG scan data out.	Secure DFT iJTAG chain
`jtag_dft_host_scan_ctrl_o`	`jtag_scan_ctrl_t`	Out	-	Non-secure DFT iJTAG scan control. Tie scan_in to scan_out if unused.	Non-secure DFT iJTAG chain
`jtag_dft_host_scan_in_i`	`logic`	In	1	Non-secure DFT iJTAG scan data in.	Non-secure DFT iJTAG chain
`jtag_dft_host_scan_out_o`	`logic`	Out	1	Non-secure DFT iJTAG scan data out.	Non-secure DFT iJTAG chain
`axi_smc_dbg_req_o`	`smc_jtag_axi_req_t`	Out	-	SMC fabric debug AXI request. Active when `JTAG_SMC_DBG_ENABLE=1`. Default: tie to '0 if disabled.	SMC `jtag_axi_in_req_i`
`axi_smc_dbg_resp_i`	`smc_jtag_axi_resp_t`	In	-	SMC fabric debug AXI response. Default: tie to '0 if disabled.	SMC `jtag_axi_in_resp_o`
`axil_smc_otp_jtag_req_o`	`smc_otp_axil_req_t`	Out	-	SMC OTP debug AXI-Lite request. Default: tie to '0 if disabled.	SMC `axil_smc_otp_jtag_req_i`
`axil_smc_otp_jtag_resp_i`	`smc_otp_axil_resp_t`	In	-	SMC OTP debug AXI-Lite response. Default: tie to '0 if disabled.	SMC `axil_smc_otp_jtag_resp_o`
`axil_sep_otp_jtag_req_o`	`sep_otp_axil_req_t`	Out	-	SEP OTP debug AXI-Lite request. Default: tie to '0 if disabled.	SEP `axil_sep_otp_jtag_req_i`
`axil_sep_otp_jtag_resp_i`	`sep_otp_axil_resp_t`	In	-	SEP OTP debug AXI-Lite response. Default: tie to '0 if disabled.	SEP `axil_sep_otp_jtag_resp_o`
`stop_clks_o`	`logic`	Out	1	Clock stop output from JTAG DEBUG_CONTROL or CLA clock-stop requests via CTN.	PLL clock gates
`cla_clock_stop_en_o`	`logic`	Out	1	CLA clock stop enable from DEBUG_CONTROL register.	Clock control logic
`jtag_boot_stall_ovrd_o`	`logic`	Out	1	JTAG boot stall override enable.	Boot control
`jtag_boot_stall_o`	`logic`	Out	1	JTAG boot stall value when override is asserted.	Boot control
`jtag_ic_reset_smc_o`	`ic_reset_smc_t`	Out	`$bits(ic_reset_smc_t)`	SMC IC_RESET override slice. Struct contains `.ovrd` (override enables) and `.val` (active-low override values), each sized to match the corresponding SMC reset control struct. Tied to '0 when `JTAG_IC_RESET_SMC_ENABLE=0`.	SMC `jtag_smc_reset_ctrl_i`
`jtag_ic_reset_sep_o`	`ic_reset_sep_t`	Out	`$bits(ic_reset_sep_t)`	SEP IC_RESET override slice. Struct contains `.ovrd` (override enables) and `.val` (active-low override values), each sized to match the corresponding SEP reset control struct. Tied to '0 when `JTAG_IC_RESET_SEP_ENABLE=0`.	SEP `jtag_sep_reset_ctrl_i`
`jtag_ic_reset_ext_o`	`ic_reset_ext_t`	Out	`$bits(ic_reset_ext_t)`	External IC_RESET override slice. Struct contains `.ovrd` (override enables) and `.val` (active-low override values), each sized per integrator-defined type. Tied to '0 when `JTAG_IC_RESET_EXT_ENABLE=0`.	Integrator-defined reset overrides for logic outside the SMU
`jtag_ptap_state_o`	`tap_state_e`	Out	-	Current PTAP TAP state.	Debug infrastructure
`jtag_ptap_inst_decoded_o`	`jtag_instruction_decoded_e`	Out	-	Current decoded PTAP instruction.	Debug infrastructure
`axil_xtrig_req_i`	`xtrig_axil_req_t`	In	-	Cross trigger CSR AXI-Lite request from SMC.	SMC `axil_dtp_csr_req_o`
`axil_xtrig_resp_o`	`xtrig_axil_resp_t`	Out	-	Cross trigger CSR AXI-Lite response to SMC.	SMC `axil_dtp_csr_resp_i`
`xtrig_ctm_src_req_o`	`logic`	Out	`[XTRIG_NUM_INT_CT-1:0]`	Cross trigger source requests from CTM to destination sinks.	Cross trigger sinks
`xtrig_ctm_src_ack_i`	`logic`	In	`[XTRIG_NUM_INT_CT-1:0]`	Cross trigger source acknowledges. Unused in pulse-sync mode (mode bit = 0). Default: tie to '0 in pulse-sync mode.	Cross trigger sinks
`xtrig_ctm_dst_req_i`	`logic`	In	`[XTRIG_NUM_INT_CT-1:0]`	Cross trigger destination requests from source generators. Default: tie to '0 if unused.	Cross trigger sources
`xtrig_ctm_dst_ack_o`	`logic`	Out	`[XTRIG_NUM_INT_CT-1:0]`	Cross trigger destination acknowledges. Unused in pulse-sync mode (mode bit = 0).	Cross trigger sources
`xtrig_clk_stop_req_i`	`logic`	In	`[XTRIG_NUM_CLK_STOP_REQ-1:0]`	Clock stop requests from CLAs or other devices in the chiplet. Default: Tie to '0 if unused.	Clock stop requesters
`xtrig_ctp_req_out_dout_o`	`logic`	Out	`[XTRIG_NUM_CTP-1:0]`	CTP request-out data output (to pad ring).	GPIO pad ring
`xtrig_ctp_req_out_dout_en_o`	`logic`	Out	`[XTRIG_NUM_CTP-1:0]`	CTP request-out output enable.	GPIO pad ring
`xtrig_ctp_req_out_din_i`	`logic`	In	`[XTRIG_NUM_CTP-1:0]`	CTP request-out loopback input. Default: tie to '0 if unused.	GPIO pad ring
`xtrig_ctp_req_out_din_en_o`	`logic`	Out	`[XTRIG_NUM_CTP-1:0]`	CTP request-out input enable.	GPIO pad ring
`xtrig_ctp_req_in_dout_o`	`logic`	Out	`[XTRIG_NUM_CTP-1:0]`	CTP request-in data output.	GPIO pad ring
`xtrig_ctp_req_in_dout_en_o`	`logic`	Out	`[XTRIG_NUM_CTP-1:0]`	CTP request-in output enable.	GPIO pad ring
`xtrig_ctp_req_in_din_i`	`logic`	In	`[XTRIG_NUM_CTP-1:0]`	CTP request-in data input. Default: tie to '0 if unused.	GPIO pad ring
`xtrig_ctp_req_in_din_en_o`	`logic`	Out	`[XTRIG_NUM_CTP-1:0]`	CTP request-in input enable.	GPIO pad ring
`xtrig_ctp_ack_in_dout_o`	`logic`	Out	`[XTRIG_NUM_CTP-1:0]`	CTP ack-in data output.	GPIO pad ring
`xtrig_ctp_ack_in_dout_en_o`	`logic`	Out	`[XTRIG_NUM_CTP-1:0]`	CTP ack-in output enable.	GPIO pad ring
`xtrig_ctp_ack_in_din_i`	`logic`	In	`[XTRIG_NUM_CTP-1:0]`	CTP ack-in data input. Default: tie to '0 if unused.	GPIO pad ring
`xtrig_ctp_ack_in_din_en_o`	`logic`	Out	`[XTRIG_NUM_CTP-1:0]`	CTP ack-in input enable.	GPIO pad ring
`xtrig_ctp_ack_out_dout_o`	`logic`	Out	`[XTRIG_NUM_CTP-1:0]`	CTP ack-out data output.	GPIO pad ring
`xtrig_ctp_ack_out_dout_en_o`	`logic`	Out	`[XTRIG_NUM_CTP-1:0]`	CTP ack-out output enable.	GPIO pad ring
`xtrig_ctp_ack_out_din_i`	`logic`	In	`[XTRIG_NUM_CTP-1:0]`	CTP ack-out data input. Default: tie to '0 if unused.	GPIO pad ring
`xtrig_ctp_ack_out_din_en_o`	`logic`	Out	`[XTRIG_NUM_CTP-1:0]`	CTP ack-out input enable.	GPIO pad ring
`test_en_i`	`logic`	In	1	DFT test-mode enable (active high) for the JTAG2AXI bridges and the cross trigger CSR crossbar. Default: 0 in functional mode.	DFT controller
`scan_rst_ni`	`logic`	In	1	DFT scan reset (active low). Unused: DTP has no reset synchronizer, so `rst_n_i` must arrive scan-controlled.	DFT controller, or tie high