Entropy Source

The entropy source uses 12 independent ring oscillators as its noise source. Each ring oscillator is constructed from the shared OCAH primitives (prim_clock_nand2, prim_buf, prim_stdmux2) to preserve the asynchronous feedback-loop structure through technology mapping. Each oscillator has two configurable lengths: a TOTAL_LENGTH and a TAPPED_LENGTH, where a multiplexer selects between the short and long feedback paths. The entropy_rosc_tune_fsm toggles between these two lengths on a rising edge of any health test failure, providing a rudimentary frequency detuning mechanism.

The oscillator output is sampled by a metastable D flip-flop (prim_flop) clocked by a sampling clock. The sampled bit is then synchronized to the system clock domain through a two-stage synchronizer. Each lane can be clocked either by an external sampling clock (rosc_sample_clk_i) or by a shared internal ring oscillator (total length 109, tapped length 53). A per-lane ripple divider provides division ratios of 1, 2, 4, 8, 16, and 32, selected through the CSR. Both selects are clock mux cells. Software changes a lane’s source or division only while that generator is disabled. A division value outside 0-5 selects divide-by-4.

Entropy source ring-oscillator complex shows the ring oscillators, sampling paths, and clock selection used to generate noise.

Entropy source ring-oscillator complex has three bands. The top band builds one sample clock per lane: RING_OSC_CTRL.SAMPLE_CLK_SELECT bit i chooses rosc_sample_clk_i (0) or the shared ring oscillator (1), and GENERATOR_i_SAMPLE_CLK_CONFIG.SAMPLE_CLK_DIVIDE picks one ripple-divider tap. The middle band is one of the twelve noise lanes; when CTRL.AUTOTUNE_ENABLE is set the lane detune follows the auto-tune FSM, otherwise RING_OSC_TUNE.DETUNE bit i. The bottom band is the ring oscillator used both in each lane and, with 109 and 53 stages, as the shared sampling oscillator. Green lines carry asynchronous oscillator signals, brown lines are in the sample-clock domain and grey lines are in the clk_i domain or are controls. Noise ring-oscillator lengths per lane lists the lane ring lengths.

Each sampled noise bit enters a serial decorrelator (entropy_decorrelator), which shifts bits through a 29-stage shift register with XOR feedback from the last stage, as Entropy source decorrelator shows. A downsample counter reloaded from DECORRELATOR_CTRL.SAMPLE_CLK_DIV latches the top 8 bits of the shift register as an entropy byte every SAMPLE_CLK_DIV + 1 clk_i cycles, 64 cycles at the reset value of 63, and pulses the byte-valid strobe for one cycle. The byte is ANDed with DECORRELATOR_MASK.ENTROPY_BYTE_MASK, so a cleared mask bit reads as zero; the mask and the divider are shared by all 12 lanes. Setting a lane’s bit in DECORRELATOR_CTRL.BYPASS forces the feedback to zero, so raw noise bits shift through the chain unmixed; the byte is still taken from the top 8 stages, downsampled and masked.

Entropy source decorrelator shows one lane’s decorrelator. The chain shifts on every clk_i cycle while enable_i is high, and the eight taps from ff_stage[21] to ff_stage[28] join into one byte-wide bundle. The output register loads when the counter reaches zero. While enable_i is low, the chain holds its contents and the counter reloads from sample_clk_div_i.

The 12 decorrelated byte streams are combined by the Barak-Impagliazzo-Wigderson (BIW) stage, which uses four gf_muladd instances performing y = a*b + c in GF(2^8) with the AES field polynomial (0x1B). The 12 input bytes are grouped into three sets of four and reduced to a single 32-bit word. This mixing step improves the statistical independence of the output without introducing significant latency.

With CTRL.BYPASS_ENTROPY_COMPRESSOR set, the BIW stage is skipped and each selected decorrelator output reaches the output select as three 32-bit words, written to the FIFO in the order word 0, word 1, word 2. Word n carries the bytes of generators 4n to 4n+3, with generator 4n+k in bits [8k+7:8k]: word 0 is {generator 3, generator 2, generator 1, generator 0}, with generator 0 in bits [7:0], word 1 carries generators 7 to 4 and word 2 generators 11 to 8. All three words come from the same decorrelator output.

Health tests operate at two levels. Each of the 12 entropy_generator instances runs an 8-bit entropy_health_test on its individual decorrelated output. At the top level, a second 32-bit entropy_health_test instance monitors the post-BIW (or post-bypass) stream.

The health test wrapper instantiates three OpenTitan-derived test modules. The repetition count test (entropy_src_repcnt_ht) tracks consecutive identical values per bit lane and flags when a threshold is exceeded. The adaptive proportion test (entropy_src_adaptp_ht) accumulates per-bit ones counts within a configurable window and compares the maximum and minimum lane counts against high and low thresholds. The Markov test (entropy_src_markov_ht) counts bit-pair transitions and compares to high and low thresholds at window boundaries. Window synchronization is driven by a prim_count counter in the entropy_generator_complex.

Health test thresholds, enable bits, and window sizes are all programmable through the CSR interface. Test status is reported as an 8-bit vector where bit 0 indicates a repetition count failure, bit 3 an adaptive proportion failure, and bits 4-5 Markov high/low failures.

HT_WATERMARK is one shared register whose source and maximum/minimum direction are selected by HT_WATERMARK_NUM; there is no independent storage per selector. A selector write changes which counter updates the shared register but does not clear it, so changing only the selector carries the value recorded by the previous mode.

The shared watermark is armed by a CTRL.MODULE_ENABLE 0-to-1 transition. High modes (REPCNT_HI, APT_HI, and MARKOV_HI) arm to 0x0000; low modes (APT_LO and MARKOV_LO) arm to 0xFFFF. A hardware reset restores the selector and watermark together, so a deterministic baseline requires HT_WATERMARK_NUM to be written before the MODULE_ENABLE toggle. With the reset-default MODULE_ENABLE=1, the power-on enable pulse performs the first mode-aware arm automatically.

The health-test subsystem includes a persistent-failure path that halts entropy output when failures persist beyond a programmed threshold. A saturating counter (ALERT_SUMMARY_FAIL_COUNTS.ANY_FAIL_COUNT) records one count per health-test window in which any test failed; a mid-window failure of the continuous repetition-count test is captured and counted once for that window. When the counter reaches ALERT_THRESHOLD.THRESHOLD (default 4, i.e. four failing windows, locked by FIPS_LOCK), alert_thresh_fail is asserted and the main FSM transitions through AlertState into AlertHang, halting entropy output. AlertHang persists until the FSM is reset by rst_ni or software clears CTRL.MODULE_ENABLE. The event sets MAIN_SM_STATUS.ALERT and raises INTR_STATUS.PERSISTENT_FAILURE. The sticky MAIN_SM_STATUS.ALERT and MAIN_SM_STATUS.ERR status bits are cleared by writing 1 (W1C) or by the full entropy-source reset.

Setting ALERT_THRESHOLD.THRESHOLD to zero disables the comparator, leaving the counter accumulating without ever asserting alert_thresh_fail.

When the SHA-256 whitener is enabled via the CSR, the 32-bit BIW output stream feeds into the entropy_sha256_whitener module. This module accumulates 16 consecutive 32-bit words (one SHA-256 block of 512 bits), computes the SHA-256 digest using the OpenTitan prim_sha2_32 primitive, and emits the 8-word (256-bit) digest. The compression ratio is 2:1 (16 input words produce 8 output words). When the whitener is disabled, the BIW output passes through to the FIFO without modification.

The conditioned entropy stream is stored in a 64-entry FIFO (entropy_fifo). Each entry is 36 bits wide: 32 data bits plus 4 byte-wise odd parity bits. The FIFO includes pointer integrity checking (normal and inverted pointer pairs with mismatch detection) and parity verification on reads. An optional churn mode XORs the incoming data with a word read from the diametrically opposite FIFO position, improving entropy distribution. Overflow, underflow, parity error, and pointer error conditions are all reported to the CSR block and can trigger interrupts.

The entropy_stream_data_o and entropy_stream_vld_o top-level ports carry each word as it is written into the FIFO, not the FIFO read data, and there is no backpressure. In SEP they connect to the DRBG seed path, which distributes the generated random data to the entropy consumers.

Because the FIFO holds the same words that seed the DRBG, FIFO_CTRL.ENABLE is covered by FIPS_LOCK. The field gates only the FIFO write, so the DRBG seed stream continues whatever its value. It resets to one, keeping the FIFO_RDATA read path live out of reset; the TRNG bring-up sequence in the Programmer’s Guide closes it before FIPS_LOCK. Reads remain available while writes are disabled, so words already in the FIFO stay readable until they are drained. The access gate in FIFO Access Gate sits on top of both fields: while it is closed, the FIFO neither captures nor reads out, whatever FIFO_CTRL.ENABLE holds.

Three FIFOs are readable through the register block, and each exposes entropy that must not leave the block in the field. The output FIFO holds the words that seed the DRBG. The two observe FIFOs hold entropy ahead of conditioning, which SP 800-90B treats as a validation-time interface that may be disabled in the field. FIPS_LOCK freezes their capture enables until reset, but only once it is set. A single access enable from the integration gates all three in hardware, whatever the register configuration holds.

Readable FIFOs lists the three FIFOs and the condition under which each captures while access is enabled.

While access is enabled, a read of a data register pops one word and the capture conditions above apply unchanged. While access is disabled:

The gate is independent of FIPS_LOCK: the lock freezes the capture enables, the gate decides whether the FIFOs capture and read out at all, and both apply. The integration decides when the access enable is asserted; SEP derives it from the lifecycle controller, as the SEP TRNG chapter describes.

The entropy source rst_ni input resets its register block, health-test/FSM state, conditioning pipeline, counters, and FIFOs. Reserved CTRL[0] reads as zero and ignores writes.

At SEP integration level, SEP_RESET_CTRL.SW_RESET_N.TRNG_SW_RST_N requests a shared reset of the entropy source and DRBG. Hardware first drains and isolates the ESRC, CSRNG, and EDN AXI ports, then asserts the common reset. This is a full-IP reset: all entropy-source CSRs and FIPS_LOCK return to reset values. Post-mux EDN adapters and the fabric entropy pool remain in the POR reset domain; they synchronously clear buffered entropy while the internal reset is active. After reset release, MODULE_ENABLE returning to one produces the normal enable pulse and restarts startup health testing before entropy is released.

DEBUG_CTRL.SELECT_SIGNAL routes one of 256 internal signals to the signal_monitor_o output, and DEBUG_CTRL.SELECT_FREQ_DIV divides it down for external observation. Some selections expose entropy ahead of conditioning: the raw per-generator noise bits, the compressed 32-bit entropy stream, and the uncompressed per-generator entropy bytes.

Both fields are covered by FIPS_LOCK: once FIPS_LOCK.LOCK is set, software can no longer retarget the pin or change its divider, so a locked, certified part cannot route pre-conditioning entropy to the observation pin. The raw and BIW observe-FIFO capture enables (NOISE_OBS_CTRL.RAW_ENABLE, BIW_OBS_CTRL.RAW_ENABLE) are held under the lock the same way, and the FIFOs themselves sit behind the access gate in FIFO Access Gate. SP 800-90B treats this pre-conditioning observation as a validation-time interface that may be disabled in the field, which the lock and the gate enforce. As defense in depth, SEP also leaves signal_monitor_o unconnected and false-paths the port in synthesis; an integration that routes the pin off-chip still owns restricting access to the lifecycle or debug states in which observing pre-conditioning entropy is acceptable.