Clocks and Resets

The two figures split the SMC clock tree at its subsystem instances. Each clock input enters on the left in its own colour, with one arrow into each of u_smc_base, u_smc_cpu_wrapper and u_smc_peripherals that it reaches; an arrow into an instance means the clock reaches the logic inside it. Each box is an RTL instance, tinted with the colour of the clock that runs it, and a box split into bands runs on several clocks. A clock gate is drawn as a CG tab coloured by the clock it gates, with the gate’s instance name in italics. A dashed arrow runs from the gate to every instance its gated clock reaches, branching at a junction dot. A count such as ×16 is the number of instances a generate loop creates. A box that no gate arrow reaches runs on the ungated clock.

Most gates in u_smc_base are activity-based: each watches the AXI or AXI-Lite port of the logic it clocks and stops the clock once the port has been idle for the programmed hysteresis. Each filter and remap register gate clocks the AXI-Lite demux in front of its register set as well as the registers, and each filter gate also clocks the error slave that answers writes to a locked filter. u_fabric_cg and the instances inside the dashed outline exist only when NO_ADDR_REMAP is 0, the default in smc_config_pkg. u_dfd_clk_gate clocks the debug bus muxes, u_dfd_top and u_ref_cnt_sync, which receives the Gray-coded count of the reference counter beside u_ref_rst_sync and forms the CLA time tick. u_axi_clk_gater clocks logic written directly in u_zeroer rather than an instance.

u_debug_clock_gate runs the debug module clock, the debug_clock port of u_digital_top, while the debugger holds dmactive. The I2C, UART, I3C, AVSBus and telemetry gates are controlled by CLOCK_GATE_CONTROL in u_smc_base. u_smc_peripherals_cdc is drawn as one row per synchroniser or CDC instance, or per group of instances that cross the same way, with the source clock on the left half and the destination clock on the right half. The clock-gate enable synchronisers carry each enable into the ungated clock of the gate it controls. u_ndmreset_request_sync has no source clock: ndmreset_request_i is asynchronous.

Each of the five peripheral enables also steers that peripheral’s leg of the register crossbar into an error slave (u_avsbus_access_gate, u_i2c_access_gate, u_uart_access_gate, u_telemetry_access_gate and u_i3c_access_gate in u_smc_peripherals, all on clk_smc_i): while the enable is set, a read of the gated peripheral’s window completes with SLVERR and data 0xBADCAB1E and a write completes with SLVERR, instead of waiting on a register block whose clock has stopped. The leg is redirected as soon as the CLOCK_GATE_CONTROL write completes; an access the peripheral has already accepted finishes there, since its clock stops only after the enable has crossed into its domain.

The AVSBus clock starts at u_avs_clk_ref_gater and u_avs_clk_periph_gater, which drive the clk_ref_i and clk_reg_i ports of u_avsbus_controller. Inside it, u_refclk_clkgate and u_apbclk_clkgate feed the glitch-free mux u_refclk_apbclk_mux, selected by avs_clock_select[1]. The test mux u_test_clkmux2_0 takes that output on clk0_i and the test clock input clk_test_i on clk1_i, and selects the test clock in test mode; u_smc_peripherals connects clk_test_i to clk_periph_i. The divider u_clk_div, used while avs_clock_select[0] is set, divides by a programmable value, 4 after reset, and u_avs_bus_clkgate stops the result on idle. The output, avs_clock, leaves through u_smc_padring on GPIO 49. spi_clk_i reaches only the SPI pad datapath in u_smc_padring.

Reset inputs enter on the left and the unit’s outputs leave on the right. Each reset net has its own colour, listed in the legend. The blue mux symbols are JTAG override muxes: jtag_reset_ctrl_i drives their input 1 and select, drawn as short stubs, and each mux passes the value on input 1 while its override bit is set.

In u_smc_reset_ctrl, powergood_i is stretched by 32 reference clock cycles into powergood_stable, which leaves as powergood_stable_o, clears the de-glitchers while low and holds the cold-reset extender. The cold reset, after its JTAG override, must stay low for 32 reference clock cycles to pass the de-glitcher, and its release is extended by 255 cycles. The cool-reset pin passes its own 32-cycle de-glitcher. The primary reset is the AND of the stable cold reset, the de-glitched cool-reset pin and the FLR cool reset. The watchdog reset is the AND of rst_ext_wdt_ni, which comes from the SEP watchdog, and the inverted SMC watchdog second timeout; smc_wdt_first_timeout_i does not reach the reset logic. The warm reset is the AND of the watchdog reset, the primary reset and the fuse reset, which the eFuse wrapper releases once fuse sensing completes and any boot stall ends. Debug-initiated resets are the JTAG overrides of the cold, cool, warm, fuse and per-subsystem resets.

u_smc_reset_sync gives each output an asynchronous assertion and a deassertion synchronised to its clock. u_smc_cool_reset_wrap runs the FLR sequence and isolation logic described in Function Level Reset and Isolation. Its gates act on each of the 32 bits; the inputs labelled SMCEN, REG and PINEN are the ISOLATE_REQ_SMCEN_REG, ISOLATE_REQ_REG and ISOLATE_REQ_PINEN_REG bits. skip_mem_repair_o is high while the synchronised isolation pin or ISOLATE_REQ_SMC is set. u_reset_unit_reg is reset by rst_primary_smc_clk_no, as are the SS_CONFIG and SS_COLD_RESET_N registers in u_smc_subsystem_resets; the isolation registers and FLR counters are reset only by the stable cold reset, so they survive a cool reset. The per-subsystem cold and warm resets leave ss_reset_ctrl_o unsynchronised, and each subsystem synchronises them. In test mode, scan_rst_ni replaces the stretched powergood, the de-glitched cold reset and every synchroniser output.

PCIe cfg_flr_pf_active_i crosses independently into the SMC and reference clock domains. Its synchronized rising edge sets the SMC isolation latch and starts the reference-domain reset sequence when enabled by a nonzero hold count. The reset state machine has no isolation-complete input: its delay must be chosen to accommodate the system’s isolation requirements.

The reset unit exports cold/warm reset, force-to-reference-clock and configuration, SRAM, debug and critical-signal hold controls for 32 subsystems. These are requests to the receiving subsystem, whose implementation defines the retained state. SS_CONFIG_LOCK and SS_COLD_RESET_LOCK mask writes to the corresponding configuration and cold-reset bits. SS_RESET_COMPLETE samples the return vector through a three-stage synchronizer; the unit does not sequence releases from it. The subsystem reset sequences are in the Programmer’s Guide.

SMC blocks have their own clock-gating enables, activity detection and hysteresis controls. For example, DMA uses a six-bit hysteresis input and bus-aware wakeup. A gate suppresses clock transitions; it does not itself create a power island or establish that outstanding bus traffic is drained. Follow the owning block’s quiescence requirements before reset, isolation or clock changes. The I2C, UART, I3C, AVSBus and telemetry windows answer SLVERR with read data 0xBADCAB1E while their CLOCK_GATE_CONTROL enable is set, so software can detect an access to a gated peripheral rather than stall on it; the other gated blocks wake on bus activity and need no such response.