Watchdog Timers

1. Operation

Each CPU core includes a dedicated watchdog timer (at 0xC000_0000 + N * 0x400), providing per-core timeout monitoring. Reset effects are described in Clocks and Resets. Base addresses and interrupt-related context for the WDT are summarized in Interrupts.

Timeouts are configurable to suit different workloads, and staged warnings (followed by reset) allow software intervention before hardware reset is triggered.

Watchdog monitoring can be disabled during debugging to prevent false triggers, supporting uninterrupted development and troubleshooting.

The watchdog interrupt is CTRL.wdogip0. Hardware sets it on every cycle the scaled count is at or above CMP, so it cannot be cleared while that holds. Feeding the watchdog resets the count but leaves wdogip0 set. The watchdog interrupt clear sequence is in the Programmer’s Guide.

1.1. Register Access

Each watchdog is locked out of reset, and a write to any register other than KEY locks it again. Software changes one register at a time:

Write 0x51F15E to KEY. KEY reads 1 while the watchdog is unlocked.
Write the target register. The watchdog locks again on this write, so the next write needs a new KEY write first.

A write acts only when its byte enables cover the register’s width, and a narrower write completes with an OKAY response without changing anything, so software cannot detect a dropped write from the response. Software uses 32-bit stores for every register except CTRL, which accepts byte writes. The Detailed Register Map below gives the width each register requires.

2. Memory Map and Register Reference

2.1. Memory Map

Register offsets are relative to the block base in the subsystem memory map. The detailed map below defines each register and its fields.

2.2. Detailed Register Map

Watchdog Timer Address Map

Watchdog timer configuration, counter, compare, and feed and key registers.

A write takes effect only if its byte enables cover all four bytes of COUNT, COUNT_HI, FEED or KEY, or bytes 0 and 1 of SCALED_COUNT or CMP; each CTRL byte is written on its own. Any other write returns OKAY and changes nothing, not even the lock.

Each effective write to a register other than KEY locks the watchdog, and changes no field if it was already locked. A 64-bit write at 0x18 writes FEED and KEY together and leaves the watchdog locked.

Register List:

Address	Name	Access	Description
0x0	CTRL	RW	KEY reg must be written to before any other register in this addrmap can be written to, unlocking the WDT. After writing to another register, the WDT will be locked again, and KEY must be written to again to unlock it.
0x8	COUNT	RW	-
0xC	COUNT_HI	W	-
0x10	SCALED_COUNT	RW	-
0x18	FEED	RW	-
0x1C	KEY	RW	-
0x20	CMP	RW	-

Register Details:

CTRL

Bits	Field	Access	Reset	Description
31:29	rsvd3	R	0x0	Reserved
28	wdogip0	RW	0x0	Pending interrupt. Hardware sets this bit on every cycle the scaled count has reached the compare value. To clear it, write KEY and then write 0 to this bit while the scaled count is below the compare value. Writing FEED does not clear it.
27:14	rsvd2	R	0x0	Reserved
13	wdogcoreawake	RW	0x0	Enable WDT to only count when the core is not in reset
12	wdogenalways	RW	0x0	Enable WDT to always count. This has priority over wdogcoreawake
11:10	rsvd1	R	0x0	Reserved
9	wdogzerocmp	RW	0x0	Enable cycle counter to be reset to 0 when compare value has been reached
8	wdogrsten	RW	0x0	Enables a sticky reset signal to outputted to top level, can be used for a second stage wdt
7:4	rsvd0	R	0x0	Reserved
3:0	wdogscale	RW	0x0	WDT counter scale value. Scales the current cycle count (time) by count / 2 ^ wdogscale value

COUNT

Bits	Field	Access	Reset	Description
31	Reserved	-	-	Reserved
30:0	wdogcount	RW	0x0	31 bit wdt counter registers. On write, the counter will be set to the written value, then continue counting up. KEY reg must be written to before any other register in this addrmap can be written to, unlocking the WDT. After writing to another register, the WDT will be locked again, and KEY must be written to again to unlock it.

COUNT_HI

Bits	Field	Access	Reset	Description
31:0	wdogcounthi	W	0x0	Upper word of the counter. The counter is 31 bits wide and lies entirely in COUNT, so this register has no storage and reads 0. A write covering all four bytes leaves the counter unchanged but locks the WDT, so KEY must be written again before the next write.

SCALED_COUNT

Bits	Field	Access	Reset	Description
31:16	Reserved	-	-	Reserved
15:0	wdogs	RW	0x0	Scaled value of wdt counter. (i.e. count >> wdogscale). Writing to this reg has no effect, but will lock the WDT (meaning KEY must be written to KEY reg to unlock it again). KEY reg must be written to before any other register in this addrmap can be written to, unlocking the WDT. After writing to another register, the WDT will be locked again, and KEY must be written to again to unlock it.

FEED

Bits	Field	Access	Reset	Description
31:0	wdogfeed	RW	0x0	Feed register. Writing 0xD09F00D will reset the counter value back to 0. Feeding does not clear CTRL.wdogip0. KEY reg must be written to before any other register in this addrmap can be written to, unlocking the WDT. After writing to another register, the WDT will be locked again, and KEY must be written to again to unlock it.

KEY

Bits	Field	Access	Reset	Description
31:0	wdogkey	RW	0x0	Key register. Magic key (0x51F15E) must be written to this register before a write to any other register in this addrmap. Must be written every time. Reading this reg returns 1 if key has been written to it and it is unlocked, 0 otherwise.

CMP

Bits	Field	Access	Reset	Description
31:16	Reserved	-	-	Reserved
15:0	wdogcmp0	RW	0x1000	Compare register. Value that gets compared to wdogs. KEY reg must be written to before any other register in this addrmap can be written to, unlocking the WDT. After writing to another register, the WDT will be locked again, and KEY must be written to again to unlock it.