AoU Interrupts and Errors

Table 1 lists the interrupt names, access behavior, and triggering conditions.

An interrupt that occurs when activation of the AoU Protocol layer is required. The interrupt can be cleared by writing '1' to the AOU_CORE.AOU_INIT.INT_ACTIVATE_START SFR. For details, please refer to the Interrupt description in Activation & Deactivation Flow.

An interrupt that occurs when deactivation of the AoU Protocol layer is required. The interrupt can be cleared by writing '1' to the AOU_CORE.AOU_INIT.INT_DEACTIVATE_START SFR. For details, please refer to the Interrupt description in Activation & Deactivation Flow.

An interrupt that occurs on the AXI Subordinate Interface when a B or R channel response is received with an ID that was not previously issued as a request. Each RP’s checker is enabled by AXI_SLV_ID_MISMATCH_ERR_RPn.AXI_SLV_ID_MISMATCH_EN. With that bit clear, the RP does not raise this interrupt. Program the enable only while the activation FSM is DISABLED and no AXI traffic is outstanding on that RP. For details, see AXI ID Mismatch Error.

Software can check the mismatched AXI ID by reading AOU_CORE.AXI_SLV_ID_MISMATCH_ERR_RPn. The interrupt can be cleared by writing '1' to AXI_SLV_BID_MISMATCH_ERR or AXI_SLV_RID_MISMATCH_ERR.

An interrupt that occurs on the AXI Manager Interface when a B or R channel response is received with an ID that was not previously issued as a request. This is detected by the ROOT:aou-architecture.adoc#aou-axi-transaction-splitter destination table.

Software can check the mismatched AXI ID by reading AOU_CORE.ERROR_INFO SFR. The interrupt can be cleared by writing '1' to AOU_CORE.ERROR_INFO.SPLIT_BID_MISMATCH_ERR / SPLIT_RID_MISMATCH_ERR.

An interrupt that occurs when, due to the ROOT:aou-architecture.adoc#aou-write-early-response-controller feature, a B response has already been sent through the AXI Subordinate Interface, and a subsequent actual B response arrives with an error. For details, see ROOT:aou-architecture.adoc#aou-transaction-flow----error-case.

Software can check the ID and error type of the transaction in which the error occurred by reading AOU_CORE.WRITE_EARLY_RESPONSE SFR. The interrupt can be cleared by writing '1' to AOU_CORE.WRITE_EARLY_RESPONSE.WRITE_RESP_ERR.

An interrupt that occurs when the write-transaction watchdog of the Write Early Response Controller expires on an RP. The watchdog is enabled per RP by AOU_CORE.WRITE_EARLY_RESPONSE_RPn.WDT_EN; it counts I_CLK cycles in which neither an AW nor a B handshake occurs while the RP has writes outstanding (AW accepted, actual B from the remote die not yet received), restarts on either handshake, and expires when the count reaches AOU_CORE.WRITE_EARLY_RESPONSE_WDT_CTL.WDT_THRESHOLD (shared by all RPs). An expiry typically means the remote die stopped answering writes for which an early OKAY may already have been returned. For details, see Write-Outstanding Queue Backpressure.

Software can find the RP by reading AOU_CORE.WRITE_EARLY_RESPONSE_RPn.WDT_TRANS_TIMEOUT_ERR. The status bit is sticky; the interrupt can be cleared by writing '1' to it, and masked for all RPs with AOU_CORE.AOU_INTERRUPT_MASK.INT_EARLY_WDT_MASK (the mask gates the pin, not the status bit).

An interrupt that occurs when AOU_CORE receives an AoU protocol violation. Refer to LinkReset Error Reporting. When AOU_CORE receives a protocol violation, software must perform a software reset of AOU_CORE and re-enter the activation sequence.

An interrupt that occurs when the FDI link is lost while AoU is in use: I_INT_FSM_IN_ACTIVE falls (on AOU_TOP the FDI bringup controller left Active for LinkError, LinkReset, Disabled or Reset; Retrain and L1 keep it asserted and do not raise this interrupt) while the activation FSM is in ACTIVATE, ENABLED or DEACTIVATE, or in DISABLED with an ActivateReq already sent or received. In the same cycle the activation FSM returns to (or stays in) DISABLED, any Activate/Deactivate handshake in flight is dropped and a pending entry to ACTIVATE is cancelled (AoU specification v0.8 section 8.3.3), so no Ack timeout follows and AOU_INIT.ACTIVATE_STATE_DISABLED reads 1. A link that drops while the FSM is DISABLED with no ActivateReq outstanding does not raise it.

The status bit is AOU_CORE.AOU_INIT.INT_FDI_LINK_DOWN [12] (sticky, write 1 to clear; like every other AOU_CORE register it is cleared by AOU_SW_RESET, so the handler reads it first), and the pin can be masked with AOU_CORE.AOU_INTERRUPT_MASK.INT_FDI_LINK_DOWN_MASK [10] (the mask gates the pin, not the status bit). The handler is the LinkReset sequence of PM entry / LinkReset / LinkDisabled sequence: read AOU_INIT, AOU_CON0.AOU_SW_RESET, restart the link on the UCIe controller, reprogram the configuration registers, ACTIVATE_START.

TBD