Peripherals

UART Wrapper Address Map

Wrapper address map instantiating the per-UART log-engine blocks.

Register Arrays:

• uart_log_engine_wrap[4].uart_log_engine_ctrl.CTRL: 4 registers, base 0x0, stride 0x400
• uart_log_engine_wrap[4].uart.RBR: 4 registers, base 0x100, stride 0x400
• uart_log_engine_wrap[4].uart.IER: 4 registers, base 0x104, stride 0x400
• uart_log_engine_wrap[4].uart.IIR: 4 registers, base 0x108, stride 0x400
• uart_log_engine_wrap[4].uart.LCR: 4 registers, base 0x10C, stride 0x400
• uart_log_engine_wrap[4].uart.MCR: 4 registers, base 0x110, stride 0x400
• uart_log_engine_wrap[4].uart.LSR: 4 registers, base 0x114, stride 0x400
• uart_log_engine_wrap[4].uart.MSR: 4 registers, base 0x118, stride 0x400
• uart_log_engine_wrap[4].uart.SCR: 4 registers, base 0x11C, stride 0x400
• uart_log_engine_wrap[4].uart.ECR: 4 registers, base 0x120, stride 0x400
• uart_log_engine_wrap[4].uart.ITR: 4 registers, base 0x124, stride 0x400
• uart_log_engine_wrap[4].log_engine.CTRL: 4 registers, base 0x200, stride 0x400
• uart_log_engine_wrap[4].log_engine.LOG_REGION_SIZE: 4 registers, base 0x204, stride 0x400
• uart_log_engine_wrap[4].log_engine.LOG_REGION_ADDR: 4 registers, base 0x208, stride 0x400
• uart_log_engine_wrap[4].log_engine.LOG_WRITE_ADDR: 4 registers, base 0x210, stride 0x400
• uart_log_engine_wrap[4].log_engine.INTR_STATUS: 4 registers, base 0x214, stride 0x400
• uart_log_engine_wrap[4].log_engine.INTR_ENABLE: 4 registers, base 0x218, stride 0x400
• uart_log_engine_wrap[4].log_engine.INTR_TEST: 4 registers, base 0x21C, stride 0x400
• uart_log_engine_wrap[4].log_engine.LOG_CTRL[16]: 64 registers, base 0x240 (uart_log_engine_wrap x4 stride 0x400, LOG_CTRL x16 stride 0x4)

Register List:

Table 2. UART Wrapper Address Map register list

Address	Name	Access	Description
0x0 - 0xC00	uart_log_engine_wrap[4].uart_log_engine_ctrl.CTRL	RW	Control Register
0x100 - 0xD00	uart_log_engine_wrap[4].uart.RBR	R	Receiver Buffer Register
0x104 - 0xD04	uart_log_engine_wrap[4].uart.IER	RW	Interrupt Enable Register
0x108 - 0xD08	uart_log_engine_wrap[4].uart.IIR	R	Interrupt Identification Register
0x10C - 0xD0C	uart_log_engine_wrap[4].uart.LCR	RW	Line Control Register
0x110 - 0xD10	uart_log_engine_wrap[4].uart.MCR	RW	Modem Control Register
0x114 - 0xD14	uart_log_engine_wrap[4].uart.LSR	R	Line Status Register
0x118 - 0xD18	uart_log_engine_wrap[4].uart.MSR	R	Modem Status Register
0x11C - 0xD1C	uart_log_engine_wrap[4].uart.SCR	RW	Scratch Register
0x120 - 0xD20	uart_log_engine_wrap[4].uart.ECR	RW	Extended Control Register
0x124 - 0xD24	uart_log_engine_wrap[4].uart.ITR	RW	Interrupt Test Register
0x200 - 0xE00	uart_log_engine_wrap[4].log_engine.CTRL	RW	Control Register
0x204 - 0xE04	uart_log_engine_wrap[4].log_engine.LOG_REGION_SIZE	RW	Log Region Size Register
0x208 - 0xE08	uart_log_engine_wrap[4].log_engine.LOG_REGION_ADDR	RW	Log Region Address Register
0x210 - 0xE10	uart_log_engine_wrap[4].log_engine.LOG_WRITE_ADDR	RW	Log Write Address Register
0x214 - 0xE14	uart_log_engine_wrap[4].log_engine.INTR_STATUS	RW	Interrupt Status Register
0x218 - 0xE18	uart_log_engine_wrap[4].log_engine.INTR_ENABLE	RW	Interrupt Enable Register
0x21C - 0xE1C	uart_log_engine_wrap[4].log_engine.INTR_TEST	W	Interrupt Test Register
0x240 - 0xE7C	uart_log_engine_wrap[4].log_engine.LOG_CTRL[16]	RW	Log Control Register

Register Details:

uart_log_engine_wrap[4].uart_log_engine_ctrl.CTRL

Table 3. uart_wrap.uart_log_engine_wrap[4].uart_log_engine_ctrl.CTRL fields

Bits	Field	Access	Reset	Description
31:1	Reserved	-	-	Reserved
0	UART_EN	RW	0x0	UART Enable. The hardware LSIO request of the UART's RX, TX, RTS and CTS pads: while set, the UART owns their data and direction. While clear, the UART keeps running, but its pads follow the GPIO data and direction selection like any pad without a hardware request, so TX and RTS do not reach the pins unless software forces LSIO selection.

uart_log_engine_wrap[4].uart.RBR

Table 4. uart_wrap.uart_log_engine_wrap[4].uart.RBR fields

Bits	Field	Access	Reset	Description
31:8	Reserved	-	-	Reserved
7:0	DATA	R RMOD	0x0	Received Data. Contains a received character. If FIFOs are enabled, this field points to the bottom of the RX FIFO. Otherwise, this field points to a single- byte Receiver Buffer Register.

uart_log_engine_wrap[4].uart.IER

Table 5. uart_wrap.uart_log_engine_wrap[4].uart.IER fields

Bits	Field	Access	Reset	Description
31:5	Reserved	-	-	Reserved
4	EFEI	RW	0x0	Enable FIFO Error Interrupt.
3	EDSSI	RW	0x0	Enable (Delta Status of) Modem Status Interrupt.
2	ELSI	RW	0x0	Enable (Receiver) Line Status Interrupt.
1	ETBEI	RW	0x0	Enable Transmitter Buffer Empty (Transmitter Holding Register Empty) Interrupt.
0	ERBFI	RW	0x0	Enable Receiver Buffer Full (Received Data Ready) Interrupt.

uart_log_engine_wrap[4].uart.IIR

Table 6. uart_wrap.uart_log_engine_wrap[4].uart.IIR fields

Bits	Field	Access	Reset	Description
31:8	Reserved	-	-	Reserved
7:6	FIFOS_ENABLED	R	0x0	FIFOs Enabled: * `0x0` - FIFOs are disabled * `0x3` - FIFOs are enabled
5:4	Reserved	-	-	Reserved
3:1	INTERRUPT_ID	R	0x0	Interrupt ID: * `0x7` - FIFO Error Interrupt (priority 0) * `0x3` - Receiver Line Status Interrupt (priority 1) * `0x6` - Reception Timeout Interrupt (priority 2) * `0x2` - Received Data Ready Interrupt (priority 3) * `0x1` - Transmitter Holding Register Empty Interrupt (priority 4) * `0x0` - Modem Status Interrupt (priority 5)
0	INTERRUPT_PENDING	R	0x1	Interrupt Pending. Active-low.

uart_log_engine_wrap[4].uart.LCR

Table 7. uart_wrap.uart_log_engine_wrap[4].uart.LCR fields

Bits	Field	Access	Reset	Description
31:8	Reserved	-	-	Reserved
7	DLAB	RW	0x0	Divisor Latch Access Bit. If set, allows access to the `DLL` and `DLM` registers when accessing addresses `0x0` and `0x4`, respectively. If unset, allows access to the `THR`, `RBR`, and `IER` registers. `IIR` and `FCR` are accessible regardless of this bit.
6	SET_BREAK	RW	0x0	Set Break. If set, forces the `tx_o` output to `0` to cause a break condition on the receiving UART.
5	STICK_PARITY	RW	0x0	Stick Parity. If set, forces the transmit and received parity bits to be `0` if even parity is selected and `1` if odd parity is selected.
4	EPS	RW	0x0	Even Parity Select: * `1` - even parity * `0` - odd parity
3	PEN	RW	0x0	Parity Enable.
2	STB	RW	0x0	Stop Bits: * `0` - 1 stop bit. * `1` - 2 stop bits. The transmitter always sends 2 stop bits; with 5-bit words the receiver checks only the first.
1:0	WLS	RW	0x0	Word Length Select: * `0x0` - 5 bits per character * `0x1` - 6 bits per character * `0x2` - 7 bits per character * `0x3` - 8 bits per character

uart_log_engine_wrap[4].uart.MCR

Table 8. uart_wrap.uart_log_engine_wrap[4].uart.MCR fields

Bits	Field	Access	Reset	Description
31:6	Reserved	-	-	Reserved
5	LINE_LOOPBACK	RW	0x0	Line Loopback. If set, the `rx_i` input is internally connected to the `tx_o` output.
4	LOOP	RW	0x0	System Loopback. If set, the transmitter is internally connected to the receiver. The `tx_o` output is set to `1`.
3	OUT2	RW	0x0	User Output 2. Writing to this bit drives the `out2_no` in the opposite polarity.
2	OUT1	RW	0x0	User Output 1. Writing to this bit drives the `out1_no` in the opposite polarity.
1	RTS	RW	0x0	Request to Send. Writing to this bit drives the `rts_no` output in the opposite polarity.
0	DTR	RW	0x0	Data Terminal Ready. Writing to this bit drives the `dtr_no` output in the opposite polarity.

uart_log_engine_wrap[4].uart.LSR

Table 9. uart_wrap.uart_log_engine_wrap[4].uart.LSR fields

Bits	Field	Access	Reset	Description
31:8	Reserved	-	-	Reserved
7	ERROR_IN_RCVR_FIFO	R	0x0	Error in Receiver FIFO. When set, indicates that the receiver FIFO or (RBR in non-FIFO mode) has the parity, framing, or break error. In other words, at least one of the PE, FE, and BI bits is set.
6	TEMT	R	0x1	Transmitter Empty. When set, indicates that the transmitter shift register and the transmitter FIFO (or THR in non-FIFO mode) are empty.
5	THRE	R	0x1	Transmitter Holding Register Empty. When set, indicates that the TX FIFO (or THR in non-FIFO mode) is empty. Clearing the Transmitter Holding Register Empty Interrupt does NOT clear this bit.
4	BI	R RC	0x0	Break Interrupt. When set, indicates that the `rx_i` input is `0` for an entire frame's time (start + data + parity + stop bits). In FIFO mode, this bit set when the character reaches the top of the receiver FIFO. In non-FIFO mode, this bit is set when the character enters the RBR. This bit triggers the Receiver Line Status Interrupt.
3	FE	R RC	0x0	Framing Error. When set, indicates that the received character is missing a stop bit. In FIFO mode, this bit is set when the character reaches the top of the FIFO. In non-FIFO mode, this bit is set when the character enters the RBR. This bit triggers the Receiver Line Status Interrupt.
2	PE	R RC	0x0	Parity Error. When set, indicates that the character at the top of the receiver FIFO (or RBR in non-FIFO mode) has a parity error. This bit triggers the Receiver Line Status Interrupt.
1	OE	R RC	0x0	Overrun Error. When set, indicates that the RX FIFO was full when a new character was received; the new character is dropped. This bit sets only in FIFO mode: in non-FIFO mode a new character overwrites an unread character in the RBR without setting it. This bit triggers the Receiver Line Status Interrupt.
0	DR	R	0x0	Data Ready. When set, indicates that the RX FIFO (or RBR in non-FIFO mode) contains data.

uart_log_engine_wrap[4].uart.MSR

Table 10. uart_wrap.uart_log_engine_wrap[4].uart.MSR fields

Bits	Field	Access	Reset	Description
31:8	Reserved	-	-	Reserved
7	DCD	R	0x0	Data Carrier Detect. This bit reflects the `dcd_ni` input in the opposite polarity, so it reads `1` while a carrier is detected.
6	RI	R	0x0	Ring Indicator. This bit reflects the `ri_ni` input in the opposite polarity, so it reads `1` while the remote modem signals an incoming call.
5	DSR	R	0x0	Data Set Ready. This bit reflects the `dsr_ni` input in the opposite polarity, so it reads `1` while the remote modem is connected and ready.
4	CTS	R	0x0	Clear to Send. This bit reflects the `cts_ni` input in the opposite polarity, so it reads `1` while the remote device is ready to receive data.
3	DDCD	R RC	0x0	Delta Data Carrier Detect. When set, indicates that the `DCD` bit has changed since the last time this register was read. This bit triggers the Modem Status Interrupt.
2	TERI	R RC	0x0	Trailing Edge Ring Indicator. When set, indicates that the `RI` bit has changed from a `1` to a `0`. This bit triggers the Modem Status Interrupt.
1	DDSR	R RC	0x0	Delta Data Set Ready. When set, indicates that the `DSR` bit has changed since the last time this register was read. This bit triggers the Modem Status Interrupt.
0	DCTS	R RC	0x0	Delta Clear to Send. When set, indicates that the `CTS` bit has changed since the last time this register was read. This bit triggers the Modem Status Interrupt.

uart_log_engine_wrap[4].uart.SCR

Table 11. uart_wrap.uart_log_engine_wrap[4].uart.SCR fields

Bits	Field	Access	Reset	Description
31:8	Reserved	-	-	Reserved
7:0	SCR	RW	0x0	Scratch. Holds user data.

uart_log_engine_wrap[4].uart.ECR

Table 12. uart_wrap.uart_log_engine_wrap[4].uart.ECR fields

Bits	Field	Access	Reset	Description
31:2	Reserved	-	-	Reserved
1:0	RCVR_TRIGGER_MS2B	RW	0x0	Receiver FIFO Trigger Level Most Significant 2 Bits. To configure the least significant 2 bits, use the `FCR.RCVR_TRIGGER` register field. The configurations for the trigger levels are: * `0x0` - 1 character * `0x1` - 4 characters * `0x2` - 8 characters * `0x3` - 14 characters * `0x4` - 32 characters * `0x5` - 64 characters * `0x6` - 128 characters * `0x7` - 256 characters * `0x8` - 512 characters * `0x9` - 1024 characters * `0xA` - 2048 characters * `0xB` - 4096 characters The Received Data Ready interrupt asserts while the receive FIFO holds at least the selected number of characters. A level above the receive FIFO depth, and any combined value above `0xB`, never asserts it.

uart_log_engine_wrap[4].uart.ITR

Table 13. uart_wrap.uart_log_engine_wrap[4].uart.ITR fields

Bits	Field	Access	Reset	Description
31:6	Reserved	-	-	Reserved
5	TRTI	RW	0x0	Test Reception Timeout Interrupt. Writing a `1` forces the interrupt and writing `0` releases it.
4	TFEI	RW	0x0	Test FIFO Error Interrupt. Writing `1` forces the interrupt and writing `0` releases it.
3	TDSSI	RW	0x0	Test (Delta Status of) Modem Status Interrupt. Writing `1` forces the interrupt and writing `0` releases it.
2	TLSI	RW	0x0	Test (Receiver) Line Status Interrupt. Writing `1` forces the interrupt and writing `0` releases it.
1	TTBEI	RW	0x0	Test Transmitter Buffer Empty (Transmitter Holding Register Empty) Interrupt. Writing `1` forces the interrupt and writing `0` releases it.
0	TRBFI	RW	0x0	Test Receiver Buffer Full (Received Data Ready) Interrupt. Writing `1` forces the interrupt and writing `0` releases it.

uart_log_engine_wrap[4].log_engine.CTRL

Table 14. uart_wrap.uart_log_engine_wrap[4].log_engine.CTRL fields

Bits	Field	Access	Reset	Description
31:1	Reserved	-	-	Reserved
0	EN	RW	0x0	Log Engine Enable. When set, enables the Log Engine. When cleared, the engine stops fetching and writing, discards buffered log data and resets transfer progress. Configuration and pending LOG_LEN values are retained, so a pending entry restarts from the start of its slot when the engine is enabled again. Clearing does not wait for outstanding bus responses.

uart_log_engine_wrap[4].log_engine.LOG_REGION_SIZE

Table 15. uart_wrap.uart_log_engine_wrap[4].log_engine.LOG_REGION_SIZE fields

Bits	Field	Access	Reset	Description
31:20	Reserved	-	-	Reserved
19:0	LOG_REGION_SIZE	RW	0x0	Log region size in bytes. Supported values are at most 512 KiB and aligned to 128 bytes (16 slots times the 8-byte fetch beat). If software programs a larger value, RTL clamps the effective region to 512 KiB. For a value that is not 128-byte aligned, RTL divides the effective region among the 16 slots and rounds each slot's transferable capacity down to complete 8-byte fetch beats. A requested LOG_LEN above that capacity is clamped to the capacity.

uart_log_engine_wrap[4].log_engine.LOG_REGION_ADDR

Table 16. uart_wrap.uart_log_engine_wrap[4].log_engine.LOG_REGION_ADDR fields

Bits	Field	Access	Reset	Description
63:56	RESERVED	R	0x0	Reserved. Reads as zero; writes are ignored.
55:32	LOG_REGION_ADDR_HI	RW	0x0	Log Region Start Address High. Contains fabric address bits [55:32].
31:0	LOG_REGION_ADDR_LO	RW	0x0	Log Region Start Address Low.

uart_log_engine_wrap[4].log_engine.LOG_WRITE_ADDR

Table 17. uart_wrap.uart_log_engine_wrap[4].log_engine.LOG_WRITE_ADDR fields

Bits	Field	Access	Reset	Description
31:0	LOG_WRITE_ADDR	RW	0x0	Log Write Address. This is the address where the log data is written to.

uart_log_engine_wrap[4].log_engine.INTR_STATUS

Table 18. uart_wrap.uart_log_engine_wrap[4].log_engine.INTR_STATUS fields

Bits	Field	Access	Reset	Description
31:5	Reserved	-	-	Reserved
4	LOG_WRITE_ERR	RW1C	0x0	Log Write Error Interrupt. Asserted when the bus for writing log data returns an error.
3:1	Reserved	-	-	Reserved
0	LOG_FETCH_ERR	RW1C	0x0	Log Fetch Error Interrupt. Asserted when the bus for fetching log data returns an error.

uart_log_engine_wrap[4].log_engine.INTR_ENABLE

Table 19. uart_wrap.uart_log_engine_wrap[4].log_engine.INTR_ENABLE fields

Bits	Field	Access	Reset	Description
31:5	Reserved	-	-	Reserved
4	LOG_WRITE_ERR	RW	0x0	Log Write Error Interrupt Enable.
3:1	Reserved	-	-	Reserved
0	LOG_FETCH_ERR	RW	0x0	Log Fetch Error Interrupt Enable.

uart_log_engine_wrap[4].log_engine.INTR_TEST

Table 20. uart_wrap.uart_log_engine_wrap[4].log_engine.INTR_TEST fields

Bits	Field	Access	Reset	Description
31:5	Reserved	-	-	Reserved
4	LOG_WRITE_ERR	W 1P	0x0	Log Write Error Interrupt Test. Writing `1` forces the interrupt.
3:1	Reserved	-	-	Reserved
0	LOG_FETCH_ERR	W 1P	0x0	Log Fetch Error Interrupt Test. Writing `1` forces the interrupt.

uart_log_engine_wrap[4].log_engine.LOG_CTRL[16]

Table 21. uart_wrap.uart_log_engine_wrap[4].log_engine.LOG_CTRL[16] fields

Bits	Field	Access	Reset	Description
31:16	Reserved	-	-	Reserved
15:0	LOG_LEN	RW	0x0	Log Length. Writing a nonzero value representing the log length in bytes to this field starts the log transfer process. The field holds the requested length until the transfer completes, when hardware clears it to zero; it is not a remaining-byte counter. There are 16 copies of this register, each representing a log entry. The log entries go through round robin arbitration.

UART Log Engine Control Address Map

Top-level enable register for the UART log-engine block.

Register List:

Table 22. UART Log Engine Control Address Map register list

Address	Name	Access	Description
0x0	CTRL	RW	Control Register

Register Details:

CTRL

Table 23. uart_log_engine_ctrl.CTRL fields

Bits	Field	Access	Reset	Description
31:1	Reserved	-	-	Reserved
0	UART_EN	RW	0x0	UART Enable. The hardware LSIO request of the UART's RX, TX, RTS and CTS pads: while set, the UART owns their data and direction. While clear, the UART keeps running, but its pads follow the GPIO data and direction selection like any pad without a hardware request, so TX and RTS do not reach the pins unless software forces LSIO selection.

UART Log Engine Wrapper Address Map

Composes the UART 16550 core, log engine, and their control registers for one UART instance.

Register Arrays:

• LOG_CTRL[16]: 16 registers, base 0x240, stride 0x4

Register List:

Table 24. UART Log Engine Wrapper Address Map register list

Address	Name	Access	Description
0x0	uart_log_engine_ctrl.CTRL	RW	Control Register
0x100	RBR	R	Receiver Buffer Register
0x104	IER	RW	Interrupt Enable Register
0x108	IIR	R	Interrupt Identification Register
0x10C	LCR	RW	Line Control Register
0x110	MCR	RW	Modem Control Register
0x114	LSR	R	Line Status Register
0x118	MSR	R	Modem Status Register
0x11C	SCR	RW	Scratch Register
0x120	ECR	RW	Extended Control Register
0x124	ITR	RW	Interrupt Test Register
0x200	log_engine.CTRL	RW	Control Register
0x204	LOG_REGION_SIZE	RW	Log Region Size Register
0x208	LOG_REGION_ADDR	RW	Log Region Address Register
0x210	LOG_WRITE_ADDR	RW	Log Write Address Register
0x214	INTR_STATUS	RW	Interrupt Status Register
0x218	INTR_ENABLE	RW	Interrupt Enable Register
0x21C	INTR_TEST	W	Interrupt Test Register
0x240 - 0x27C	LOG_CTRL[16]	RW	Log Control Register

Register Details:

uart_log_engine_ctrl.CTRL

Table 25. uart_log_engine_wrap.uart_log_engine_ctrl.CTRL fields

Bits	Field	Access	Reset	Description
31:1	Reserved	-	-	Reserved
0	UART_EN	RW	0x0	UART Enable. The hardware LSIO request of the UART's RX, TX, RTS and CTS pads: while set, the UART owns their data and direction. While clear, the UART keeps running, but its pads follow the GPIO data and direction selection like any pad without a hardware request, so TX and RTS do not reach the pins unless software forces LSIO selection.

RBR

Table 26. uart_log_engine_wrap.RBR fields

Bits	Field	Access	Reset	Description
31:8	Reserved	-	-	Reserved
7:0	DATA	R RMOD	0x0	Received Data. Contains a received character. If FIFOs are enabled, this field points to the bottom of the RX FIFO. Otherwise, this field points to a single- byte Receiver Buffer Register.

IER

Table 27. uart_log_engine_wrap.IER fields

Bits	Field	Access	Reset	Description
31:5	Reserved	-	-	Reserved
4	EFEI	RW	0x0	Enable FIFO Error Interrupt.
3	EDSSI	RW	0x0	Enable (Delta Status of) Modem Status Interrupt.
2	ELSI	RW	0x0	Enable (Receiver) Line Status Interrupt.
1	ETBEI	RW	0x0	Enable Transmitter Buffer Empty (Transmitter Holding Register Empty) Interrupt.
0	ERBFI	RW	0x0	Enable Receiver Buffer Full (Received Data Ready) Interrupt.

IIR

Table 28. uart_log_engine_wrap.IIR fields

Bits	Field	Access	Reset	Description
31:8	Reserved	-	-	Reserved
7:6	FIFOS_ENABLED	R	0x0	FIFOs Enabled: * `0x0` - FIFOs are disabled * `0x3` - FIFOs are enabled
5:4	Reserved	-	-	Reserved
3:1	INTERRUPT_ID	R	0x0	Interrupt ID: * `0x7` - FIFO Error Interrupt (priority 0) * `0x3` - Receiver Line Status Interrupt (priority 1) * `0x6` - Reception Timeout Interrupt (priority 2) * `0x2` - Received Data Ready Interrupt (priority 3) * `0x1` - Transmitter Holding Register Empty Interrupt (priority 4) * `0x0` - Modem Status Interrupt (priority 5)
0	INTERRUPT_PENDING	R	0x1	Interrupt Pending. Active-low.

LCR

Table 29. uart_log_engine_wrap.LCR fields

Bits	Field	Access	Reset	Description
31:8	Reserved	-	-	Reserved
7	DLAB	RW	0x0	Divisor Latch Access Bit. If set, allows access to the `DLL` and `DLM` registers when accessing addresses `0x0` and `0x4`, respectively. If unset, allows access to the `THR`, `RBR`, and `IER` registers. `IIR` and `FCR` are accessible regardless of this bit.
6	SET_BREAK	RW	0x0	Set Break. If set, forces the `tx_o` output to `0` to cause a break condition on the receiving UART.
5	STICK_PARITY	RW	0x0	Stick Parity. If set, forces the transmit and received parity bits to be `0` if even parity is selected and `1` if odd parity is selected.
4	EPS	RW	0x0	Even Parity Select: * `1` - even parity * `0` - odd parity
3	PEN	RW	0x0	Parity Enable.
2	STB	RW	0x0	Stop Bits: * `0` - 1 stop bit. * `1` - 2 stop bits. The transmitter always sends 2 stop bits; with 5-bit words the receiver checks only the first.
1:0	WLS	RW	0x0	Word Length Select: * `0x0` - 5 bits per character * `0x1` - 6 bits per character * `0x2` - 7 bits per character * `0x3` - 8 bits per character

MCR

Table 30. uart_log_engine_wrap.MCR fields

Bits	Field	Access	Reset	Description
31:6	Reserved	-	-	Reserved
5	LINE_LOOPBACK	RW	0x0	Line Loopback. If set, the `rx_i` input is internally connected to the `tx_o` output.
4	LOOP	RW	0x0	System Loopback. If set, the transmitter is internally connected to the receiver. The `tx_o` output is set to `1`.
3	OUT2	RW	0x0	User Output 2. Writing to this bit drives the `out2_no` in the opposite polarity.
2	OUT1	RW	0x0	User Output 1. Writing to this bit drives the `out1_no` in the opposite polarity.
1	RTS	RW	0x0	Request to Send. Writing to this bit drives the `rts_no` output in the opposite polarity.
0	DTR	RW	0x0	Data Terminal Ready. Writing to this bit drives the `dtr_no` output in the opposite polarity.

LSR

Table 31. uart_log_engine_wrap.LSR fields

Bits	Field	Access	Reset	Description
31:8	Reserved	-	-	Reserved
7	ERROR_IN_RCVR_FIFO	R	0x0	Error in Receiver FIFO. When set, indicates that the receiver FIFO or (RBR in non-FIFO mode) has the parity, framing, or break error. In other words, at least one of the PE, FE, and BI bits is set.
6	TEMT	R	0x1	Transmitter Empty. When set, indicates that the transmitter shift register and the transmitter FIFO (or THR in non-FIFO mode) are empty.
5	THRE	R	0x1	Transmitter Holding Register Empty. When set, indicates that the TX FIFO (or THR in non-FIFO mode) is empty. Clearing the Transmitter Holding Register Empty Interrupt does NOT clear this bit.
4	BI	R RC	0x0	Break Interrupt. When set, indicates that the `rx_i` input is `0` for an entire frame's time (start + data + parity + stop bits). In FIFO mode, this bit set when the character reaches the top of the receiver FIFO. In non-FIFO mode, this bit is set when the character enters the RBR. This bit triggers the Receiver Line Status Interrupt.
3	FE	R RC	0x0	Framing Error. When set, indicates that the received character is missing a stop bit. In FIFO mode, this bit is set when the character reaches the top of the FIFO. In non-FIFO mode, this bit is set when the character enters the RBR. This bit triggers the Receiver Line Status Interrupt.
2	PE	R RC	0x0	Parity Error. When set, indicates that the character at the top of the receiver FIFO (or RBR in non-FIFO mode) has a parity error. This bit triggers the Receiver Line Status Interrupt.
1	OE	R RC	0x0	Overrun Error. When set, indicates that the RX FIFO was full when a new character was received; the new character is dropped. This bit sets only in FIFO mode: in non-FIFO mode a new character overwrites an unread character in the RBR without setting it. This bit triggers the Receiver Line Status Interrupt.
0	DR	R	0x0	Data Ready. When set, indicates that the RX FIFO (or RBR in non-FIFO mode) contains data.

MSR

Table 32. uart_log_engine_wrap.MSR fields

Bits	Field	Access	Reset	Description
31:8	Reserved	-	-	Reserved
7	DCD	R	0x0	Data Carrier Detect. This bit reflects the `dcd_ni` input in the opposite polarity, so it reads `1` while a carrier is detected.
6	RI	R	0x0	Ring Indicator. This bit reflects the `ri_ni` input in the opposite polarity, so it reads `1` while the remote modem signals an incoming call.
5	DSR	R	0x0	Data Set Ready. This bit reflects the `dsr_ni` input in the opposite polarity, so it reads `1` while the remote modem is connected and ready.
4	CTS	R	0x0	Clear to Send. This bit reflects the `cts_ni` input in the opposite polarity, so it reads `1` while the remote device is ready to receive data.
3	DDCD	R RC	0x0	Delta Data Carrier Detect. When set, indicates that the `DCD` bit has changed since the last time this register was read. This bit triggers the Modem Status Interrupt.
2	TERI	R RC	0x0	Trailing Edge Ring Indicator. When set, indicates that the `RI` bit has changed from a `1` to a `0`. This bit triggers the Modem Status Interrupt.
1	DDSR	R RC	0x0	Delta Data Set Ready. When set, indicates that the `DSR` bit has changed since the last time this register was read. This bit triggers the Modem Status Interrupt.
0	DCTS	R RC	0x0	Delta Clear to Send. When set, indicates that the `CTS` bit has changed since the last time this register was read. This bit triggers the Modem Status Interrupt.

SCR

Table 33. uart_log_engine_wrap.SCR fields

Bits	Field	Access	Reset	Description
31:8	Reserved	-	-	Reserved
7:0	SCR	RW	0x0	Scratch. Holds user data.

ECR

Table 34. uart_log_engine_wrap.ECR fields

Bits	Field	Access	Reset	Description
31:2	Reserved	-	-	Reserved
1:0	RCVR_TRIGGER_MS2B	RW	0x0	Receiver FIFO Trigger Level Most Significant 2 Bits. To configure the least significant 2 bits, use the `FCR.RCVR_TRIGGER` register field. The configurations for the trigger levels are: * `0x0` - 1 character * `0x1` - 4 characters * `0x2` - 8 characters * `0x3` - 14 characters * `0x4` - 32 characters * `0x5` - 64 characters * `0x6` - 128 characters * `0x7` - 256 characters * `0x8` - 512 characters * `0x9` - 1024 characters * `0xA` - 2048 characters * `0xB` - 4096 characters The Received Data Ready interrupt asserts while the receive FIFO holds at least the selected number of characters. A level above the receive FIFO depth, and any combined value above `0xB`, never asserts it.

ITR

Table 35. uart_log_engine_wrap.ITR fields

Bits	Field	Access	Reset	Description
31:6	Reserved	-	-	Reserved
5	TRTI	RW	0x0	Test Reception Timeout Interrupt. Writing a `1` forces the interrupt and writing `0` releases it.
4	TFEI	RW	0x0	Test FIFO Error Interrupt. Writing `1` forces the interrupt and writing `0` releases it.
3	TDSSI	RW	0x0	Test (Delta Status of) Modem Status Interrupt. Writing `1` forces the interrupt and writing `0` releases it.
2	TLSI	RW	0x0	Test (Receiver) Line Status Interrupt. Writing `1` forces the interrupt and writing `0` releases it.
1	TTBEI	RW	0x0	Test Transmitter Buffer Empty (Transmitter Holding Register Empty) Interrupt. Writing `1` forces the interrupt and writing `0` releases it.
0	TRBFI	RW	0x0	Test Receiver Buffer Full (Received Data Ready) Interrupt. Writing `1` forces the interrupt and writing `0` releases it.

log_engine.CTRL

Table 36. uart_log_engine_wrap.log_engine.CTRL fields

Bits	Field	Access	Reset	Description
31:1	Reserved	-	-	Reserved
0	EN	RW	0x0	Log Engine Enable. When set, enables the Log Engine. When cleared, the engine stops fetching and writing, discards buffered log data and resets transfer progress. Configuration and pending LOG_LEN values are retained, so a pending entry restarts from the start of its slot when the engine is enabled again. Clearing does not wait for outstanding bus responses.

LOG_REGION_SIZE

Table 37. uart_log_engine_wrap.LOG_REGION_SIZE fields

Bits	Field	Access	Reset	Description
31:20	Reserved	-	-	Reserved
19:0	LOG_REGION_SIZE	RW	0x0	Log region size in bytes. Supported values are at most 512 KiB and aligned to 128 bytes (16 slots times the 8-byte fetch beat). If software programs a larger value, RTL clamps the effective region to 512 KiB. For a value that is not 128-byte aligned, RTL divides the effective region among the 16 slots and rounds each slot's transferable capacity down to complete 8-byte fetch beats. A requested LOG_LEN above that capacity is clamped to the capacity.

LOG_REGION_ADDR

Table 38. uart_log_engine_wrap.LOG_REGION_ADDR fields

Bits	Field	Access	Reset	Description
63:56	RESERVED	R	0x0	Reserved. Reads as zero; writes are ignored.
55:32	LOG_REGION_ADDR_HI	RW	0x0	Log Region Start Address High. Contains fabric address bits [55:32].
31:0	LOG_REGION_ADDR_LO	RW	0x0	Log Region Start Address Low.

LOG_WRITE_ADDR

Table 39. uart_log_engine_wrap.LOG_WRITE_ADDR fields

Bits	Field	Access	Reset	Description
31:0	LOG_WRITE_ADDR	RW	0x0	Log Write Address. This is the address where the log data is written to.

INTR_STATUS

Table 40. uart_log_engine_wrap.INTR_STATUS fields

Bits	Field	Access	Reset	Description
31:5	Reserved	-	-	Reserved
4	LOG_WRITE_ERR	RW1C	0x0	Log Write Error Interrupt. Asserted when the bus for writing log data returns an error.
3:1	Reserved	-	-	Reserved
0	LOG_FETCH_ERR	RW1C	0x0	Log Fetch Error Interrupt. Asserted when the bus for fetching log data returns an error.

INTR_ENABLE

Table 41. uart_log_engine_wrap.INTR_ENABLE fields

Bits	Field	Access	Reset	Description
31:5	Reserved	-	-	Reserved
4	LOG_WRITE_ERR	RW	0x0	Log Write Error Interrupt Enable.
3:1	Reserved	-	-	Reserved
0	LOG_FETCH_ERR	RW	0x0	Log Fetch Error Interrupt Enable.

INTR_TEST

Table 42. uart_log_engine_wrap.INTR_TEST fields

Bits	Field	Access	Reset	Description
31:5	Reserved	-	-	Reserved
4	LOG_WRITE_ERR	W 1P	0x0	Log Write Error Interrupt Test. Writing `1` forces the interrupt.
3:1	Reserved	-	-	Reserved
0	LOG_FETCH_ERR	W 1P	0x0	Log Fetch Error Interrupt Test. Writing `1` forces the interrupt.

LOG_CTRL[16]

Table 43. uart_log_engine_wrap.LOG_CTRL[16] fields

Bits	Field	Access	Reset	Description
31:16	Reserved	-	-	Reserved
15:0	LOG_LEN	RW	0x0	Log Length. Writing a nonzero value representing the log length in bytes to this field starts the log transfer process. The field holds the requested length until the transfer completes, when hardware clears it to zero; it is not a remaining-byte counter. There are 16 copies of this register, each representing a log entry. The log entries go through round robin arbitration.

PWM Wrapper Address Map

Wrapper address map instantiating the PWM register block and its pad control.

Register Arrays:

• PWM_PARAM[4]: 4 registers, base 0x14, stride 0x4
• DUTY_CYCLE[4]: 4 registers, base 0x24, stride 0x4
• BLINK_PARAM[4]: 4 registers, base 0x34, stride 0x4

Register List:

Table 44. PWM Wrapper Address Map register list

Address	Name	Access	Description
0x0	ALERT_TEST	W	-
0x4	REGWEN	RW	-
0x8	CFG	RW	-
0xC	PWM_EN	RW	-
0x10	INVERT	RW	-
0x14 - 0x20	PWM_PARAM[4]	RW	-
0x24 - 0x30	DUTY_CYCLE[4]	RW	-
0x34 - 0x40	BLINK_PARAM[4]	RW	-
0x800	CTRL	RW	Control Register

Register Details:

ALERT_TEST

Table 45. pwm_wrap.ALERT_TEST fields

Bits	Field	Access	Reset	Description
31:1	Reserved	-	-	Reserved
0	fatal_fault	W	0x0	Write 1 to trigger one alert event of this kind.

REGWEN

Table 46. pwm_wrap.REGWEN fields

Bits	Field	Access	Reset	Description
31:1	Reserved	-	-	Reserved
0	REGWEN	RW0C	0x1	When true, all writable registers can be modified. When false, they become read-only. Defaults true, write zero to clear. This can be cleared after initial configuration at boot in order to lock in the supplied register settings.

CFG

Table 47. pwm_wrap.CFG fields

Bits	Field	Access	Reset	Description
31	CNTR_EN	RW	0x0	Assert this bit to enable the PWM phase counter. Clearing this bit disables and resets the phase counter.
30:27	DC_RESN	RW	0x7	Phase Resolution (logarithmic). All duty-cycle and phase shift registers represent fractional PWM cycles, expressed in units of 2^-16 PWM cycles. Each PWM cycle is divided into 2^(DC_RESN+1) time slices, and thus only the (DC_RESN+1) most significant bits of each phase or duty cycle register are relevant.
26:0	CLK_DIV	RW	0x8000	Sets the period of each PWM beat to be (CLK_DIV+1) input clock periods. Since PWM pulses are generated once every 2^(DC_RESN+1) beats, the period between output pulses is 2^(DC_RESN+1)*(CLK_DIV+1) times longer than the input clock period.

PWM_EN

Table 48. pwm_wrap.PWM_EN fields

Bits	Field	Access	Reset	Description
31:4	Reserved	-	-	Reserved
3:0	EN	RW	0x0	Write 1 to this bit to enable PWM pulses on the corresponding channel.

INVERT

Table 49. pwm_wrap.INVERT fields

Bits	Field	Access	Reset	Description
31:4	Reserved	-	-	Reserved
3:0	INVERT	RW	0x0	Write 1 to this bit to invert the output for each channel, so that the corresponding output is active-low.

PWM_PARAM[4]

Table 50. pwm_wrap.PWM_PARAM[4] fields

Bits	Field	Access	Reset	Description
31	BLINK_EN	RW	0x0	Enables blink (or heartbeat). If cleared, the output duty cycle will remain constant at DUTY_CYCLE.A. Enabling this bit causes the PWM duty cycle to alternate between DUTY_CYCLE.A and DUTY_CYCLE.B
30	HTBT_EN	RW	0x0	Modulates blink behavior to create a heartbeat effect. When HTBT_EN is set, the duty cycle increases (or decreases) linearly from DUTY_CYCLE.A to DUTY_CYCLE.B and back, in steps of (BLINK_PARAM.Y+1), with an increment (decrement) once every (BLINK_PARAM.X+1) PWM cycles. When HTBT_EN is cleared, the standard blink behavior applies, meaning that the output duty cycle alternates between DUTY_CYCLE.A for (BLINK_PARAM.X+1) pulses and DUTY_CYCLE.B for (BLINK_PARAM.Y+1) pulses.
29:16	Reserved	-	-	Reserved
15:0	PHASE_DELAY	RW	0x0	Phase delay of the PWM leading edge, in units of 2^(-16) PWM cycles. The leading edge will be the rising edge of the output signal unless the corresponding INVERT bit is set.

DUTY_CYCLE[4]

Table 51. pwm_wrap.DUTY_CYCLE[4] fields

Bits	Field	Access	Reset	Description
31:16	B	RW	0x7FFF	The target duty cycle for PWM output, in units of 2^(-16)ths of a pulse cycle. The actual precision is however limited to the (DC_RESN+1) most significant bits. This setting only applies when blinking, and determines the target duty cycle.
15:0	A	RW	0x7FFF	The initial duty cycle for PWM output, in units of 2^(-16)ths of a pulse cycle. The actual precision is however limited to the (DC_RESN+1) most significant bits. This setting applies continuously when not blinking and determines the initial duty cycle when blinking.

BLINK_PARAM[4]

Table 52. pwm_wrap.BLINK_PARAM[4] fields

Bits	Field	Access	Reset	Description
31:16	Y	RW	0x0	This blink-rate timing parameter has two different interpretations depending on whether or not the heartbeat feature is enabled. If heartbeat is disabled, a blinking PWM will pulse at duty cycle B for (Y+1) pulse cycles before returning to duty cycle A. If heartbeat is enabled the duty cycle will increase (or decrease) by (Y+1) units every time it is incremented (or decremented).
15:0	X	RW	0x0	This blink-rate timing parameter has two different interpretations depending on whether or not the heartbeat feature is enabled. If heartbeat is disabled, a blinking PWM will pulse at duty cycle A for (X+1) pulse cycles before switching to duty cycle B. If heartbeat is enabled the duty cycle will start at duty cycle A, but will be incremented (or decremented) every (X+1) cycles. In heartbeat mode is enabled, the size of each step is controlled by BLINK_PARAM.Y.

CTRL

Table 53. pwm_wrap.CTRL fields

Bits	Field	Access	Reset	Description
31:4	Reserved	-	-	Reserved
3:0	PAD_EN	RW	0x0	PWM Pad Function Select, one bit per channel. When bit i is set, the integration routes channel i's output to its pad. Does not start the channel; PWM_EN starts and stops each channel's waveform.

Pulse Width Modulator

Transmission of pulse-width modulated output signals with adjustable duty cycle

Register Arrays:

• PWM_PARAM[4]: 4 registers, base 0x14, stride 0x4
• DUTY_CYCLE[4]: 4 registers, base 0x24, stride 0x4
• BLINK_PARAM[4]: 4 registers, base 0x34, stride 0x4

Register List:

Table 54. Pulse Width Modulator register list

Address	Name	Access	Description
0x0	ALERT_TEST	W	-
0x4	REGWEN	RW	-
0x8	CFG	RW	-
0xC	PWM_EN	RW	-
0x10	INVERT	RW	-
0x14 - 0x20	PWM_PARAM[4]	RW	-
0x24 - 0x30	DUTY_CYCLE[4]	RW	-
0x34 - 0x40	BLINK_PARAM[4]	RW	-

Register Details:

ALERT_TEST

Table 55. pwm.ALERT_TEST fields

Bits	Field	Access	Reset	Description
31:1	Reserved	-	-	Reserved
0	fatal_fault	W	0x0	Write 1 to trigger one alert event of this kind.

REGWEN

Table 56. pwm.REGWEN fields

Bits	Field	Access	Reset	Description
31:1	Reserved	-	-	Reserved
0	REGWEN	RW0C	0x1	When true, all writable registers can be modified. When false, they become read-only. Defaults true, write zero to clear. This can be cleared after initial configuration at boot in order to lock in the supplied register settings.

CFG

Table 57. pwm.CFG fields

Bits	Field	Access	Reset	Description
31	CNTR_EN	RW	0x0	Assert this bit to enable the PWM phase counter. Clearing this bit disables and resets the phase counter.
30:27	DC_RESN	RW	0x7	Phase Resolution (logarithmic). All duty-cycle and phase shift registers represent fractional PWM cycles, expressed in units of 2^-16 PWM cycles. Each PWM cycle is divided into 2^(DC_RESN+1) time slices, and thus only the (DC_RESN+1) most significant bits of each phase or duty cycle register are relevant.
26:0	CLK_DIV	RW	0x8000	Sets the period of each PWM beat to be (CLK_DIV+1) input clock periods. Since PWM pulses are generated once every 2^(DC_RESN+1) beats, the period between output pulses is 2^(DC_RESN+1)*(CLK_DIV+1) times longer than the input clock period.

PWM_EN

Table 58. pwm.PWM_EN fields

Bits	Field	Access	Reset	Description
31:4	Reserved	-	-	Reserved
3:0	EN	RW	0x0	Write 1 to this bit to enable PWM pulses on the corresponding channel.

INVERT

Table 59. pwm.INVERT fields

Bits	Field	Access	Reset	Description
31:4	Reserved	-	-	Reserved
3:0	INVERT	RW	0x0	Write 1 to this bit to invert the output for each channel, so that the corresponding output is active-low.

PWM_PARAM[4]

Table 60. pwm.PWM_PARAM[4] fields

Bits	Field	Access	Reset	Description
31	BLINK_EN	RW	0x0	Enables blink (or heartbeat). If cleared, the output duty cycle will remain constant at DUTY_CYCLE.A. Enabling this bit causes the PWM duty cycle to alternate between DUTY_CYCLE.A and DUTY_CYCLE.B
30	HTBT_EN	RW	0x0	Modulates blink behavior to create a heartbeat effect. When HTBT_EN is set, the duty cycle increases (or decreases) linearly from DUTY_CYCLE.A to DUTY_CYCLE.B and back, in steps of (BLINK_PARAM.Y+1), with an increment (decrement) once every (BLINK_PARAM.X+1) PWM cycles. When HTBT_EN is cleared, the standard blink behavior applies, meaning that the output duty cycle alternates between DUTY_CYCLE.A for (BLINK_PARAM.X+1) pulses and DUTY_CYCLE.B for (BLINK_PARAM.Y+1) pulses.
29:16	Reserved	-	-	Reserved
15:0	PHASE_DELAY	RW	0x0	Phase delay of the PWM leading edge, in units of 2^(-16) PWM cycles. The leading edge will be the rising edge of the output signal unless the corresponding INVERT bit is set.

DUTY_CYCLE[4]

Table 61. pwm.DUTY_CYCLE[4] fields

Bits	Field	Access	Reset	Description
31:16	B	RW	0x7FFF	The target duty cycle for PWM output, in units of 2^(-16)ths of a pulse cycle. The actual precision is however limited to the (DC_RESN+1) most significant bits. This setting only applies when blinking, and determines the target duty cycle.
15:0	A	RW	0x7FFF	The initial duty cycle for PWM output, in units of 2^(-16)ths of a pulse cycle. The actual precision is however limited to the (DC_RESN+1) most significant bits. This setting applies continuously when not blinking and determines the initial duty cycle when blinking.

BLINK_PARAM[4]

Table 62. pwm.BLINK_PARAM[4] fields

Bits	Field	Access	Reset	Description
31:16	Y	RW	0x0	This blink-rate timing parameter has two different interpretations depending on whether or not the heartbeat feature is enabled. If heartbeat is disabled, a blinking PWM will pulse at duty cycle B for (Y+1) pulse cycles before returning to duty cycle A. If heartbeat is enabled the duty cycle will increase (or decrease) by (Y+1) units every time it is incremented (or decremented).
15:0	X	RW	0x0	This blink-rate timing parameter has two different interpretations depending on whether or not the heartbeat feature is enabled. If heartbeat is disabled, a blinking PWM will pulse at duty cycle A for (X+1) pulse cycles before switching to duty cycle B. If heartbeat is enabled the duty cycle will start at duty cycle A, but will be incremented (or decremented) every (X+1) cycles. In heartbeat mode is enabled, the size of each step is controlled by BLINK_PARAM.Y.

PWM Control Address Map

Per-channel pad-function select for the PWM outputs.

Register List:

Table 63. PWM Control Address Map register list

Address	Name	Access	Description
0x0	CTRL	RW	Control Register

Register Details:

CTRL

Table 64. pwm_ctrl.CTRL fields

Bits	Field	Access	Reset	Description
31:4	Reserved	-	-	Reserved
3:0	PAD_EN	RW	0x0	PWM Pad Function Select, one bit per channel. When bit i is set, the integration routes channel i's output to its pad. Does not start the channel; PWM_EN starts and stops each channel's waveform.