Log Engine

The Log Engine sends memory-resident messages to a UART without a CPU copying each byte. Software supplies one memory region, divided into 16 slots, and submits each message by writing its slot’s length. The engine selects pending slots in round-robin order and completes one message before moving to the next.

A 64-bit AXI4-Lite read path fetches message data into a FIFO. A separate 32-bit AXI4-Lite write path sends one character at a time to a fixed UART address, paced by uart_tx_ready_i. The register interface is also 32-bit AXI4-Lite. Fetch addresses are 56 bits; UART addresses are 32 bits. The Log Engine section of the Programmer’s Guide gives the configuration, submission and recovery procedures.

Figure 1 shows the SMC wrapper and its memory-to-UART data paths. Parentheses after an instance name give its module or, for a block taken from another project, that project: the demuxes, the mux and the axi_lite_from_mem converters come from PULP, and u_uart_core, u_arbiter_tree and u_rdata_fifo from OpenTitan. uart_log_engine_wrap runs on one clock, clk_i. Its register port, with 32-bit address and data, comes from uart_wrap, and the demux u_csr_axi_lite_demux decodes it by base and size onto four maps: the UART, the log engine, the control block and an error slave that answers DECERR. The control block u_uart_log_engine_ctrl_reg, generated by PeakRDL from uart_log_engine_ctrl.rdl, drives uart_en_o from CTRL.UART_EN.

The UART register path and the log engine’s write path share the UART’s register port through the mux u_log_write_axi_lite_mux: port 0 carries register accesses and port 1 the log engine’s writes. Inside u_uart_16550, the demux u_axi_lite_demux selects one of three PeakRDL register blocks. While LCR.DLAB is set, DLL and DLM go to the divisor-latch block (dl); writes to THR and FCR go to the write-only block (main_wo); everything else goes to the main block. u_uart_core holds the TX and RX FIFOs, the transmitter and the receiver, and passes uart_rx_i and the modem inputs through two-flop synchronizers, marked by the synchronizer badge on its edge.

The dashed outline marks the log engine, which exists only when GEN_LOG_ENGINE is set; without it the log-fetch port is driven to zero and log_engine_irq_o is low. u_log_engine_reg, generated from log_engine.rdl, holds the 16 LOG_CTRL registers and the interrupt registers, and drives log_engine_irq_o. u_arbiter_tree picks a log entry whose LOG_LEN is non-zero and gives its index and length to the log fetch FSM. The fetch FSM reads 64-bit words through the axi_lite_from_mem converter u_axil_lite_from_log_fetch_fsm on the log-fetch port, which has 56-bit address and 64-bit data, into u_rdata_fifo, whose depth is FIFO_DEPTH (4 in the SMC). The log write FSM takes one byte at a time from the FIFO and writes it, through a second converter, u_axi_lite_from_log_write_fsm, to LOG_WRITE_ADDR over a 32-bit AXI4-Lite port. It waits for uart_txrdy_o before each write.

The parameters and ports of log_engine are listed in log_engine.

A shared clk_i and active-low asynchronous rst_ni drive all interfaces and internal logic. The CSR AXI4-Lite slave (csr_axil_req_i / csr_axil_resp_o) carries register traffic; two AXI4-Lite initiators carry memory reads (log_fetch_axil_req_o / log_fetch_axil_resp_i) and UART writes (log_write_axil_req_o / log_write_axil_resp_i). Both initiator adapters use PROT = 3’b010 (non-secure, unprivileged data) and allow one outstanding request each. They issue no bursts.

uart_tx_ready_i permits the write FSM to request the next character transfer. The UART integration supplies readiness in the engine’s clock domain and must account for writes already accepted by the bus. See Section 2.2 for the write data and strobe behavior.

irq_o is the active-high OR of enabled, latched fetch and write error status.