Referenced Documents

This appendix collects the companion guides, specifications and external design documentation referenced by the subsystem and IP chapters. Revisions below are those cited in this manual; an unspecified revision does not imply the latest edition.

1. OCAH Documentation

Table 1 identifies the companion guides used for integration and programming details.

Table 1. OCAH documentation references
Document	Referenced for
Open Chiplet Atlas Harness (OCAH) Integrator Guide	Subsystem integration and external interfaces, including the SEP external TRNG aperture’s register decode and error-response requirements.

2. OCA Specifications

Table 2 identifies the OCA specifications cited by this manual.

Table 2. OCA specification references
Document	Referenced for
Open Chiplet Cross Triggering (OCCT) specification	DTP cross-trigger fabric, Cross-Trigger Network and Cross-Trigger Port. The cited revision and a document-specific URL are not specified in this manual.
Open Chiplet Atlas specification: Open Chiplet Time Synchronization (OCTS)	System Timer OCTS protocol and credit-based synchronization. The cited revision is not specified in this manual.
AXI-over-UCIe (AoU) specification	AoU bridge protocol. The imported AoU microarchitecture specification cites revision 0.7 (2025).

3. Interface and Security Standards

Table 3 identifies the standards used by the interfaces and security functions.

Table 3. Interface and security standard references
Document	Referenced for
Universal Chiplet Interconnect Express (UCIe) specification	AoU FDI interface, flit cancellation and stall handling. The cited revision is not specified in this manual.
IEEE 1149.1-2013	DTP JTAG TAPs, instruction registers and IC_RESET test data register.
IEEE 1838-2019	DTP hierarchical multi-chiplet test access and STAP 3D control register.
IEEE 1687-2014	DTP iJTAG instrumentation and segment insertion bits (SIBs).
I2C-bus specification, revisions 6 and 7.0	I2C controller. The feature overview cites revision 7.0; the architecture chapter cites revision 6 for electrical and timing requirements.
System Management Bus (SMBus) specification, revision 3.2	I2C controller SMBus operation.
Power Management Bus (PMBus) specification, revision 1.4	I2C controller PMBus operation.
AVSBus specification, version 1.3.1	AVSBus controller voltage-scaling frames and responses.
MIPI I3C Basic specification, versions 1.0 and 1.1.1	I3C core controller interface.
MIPI I3C HCI (Host Controller Interface) specification, version 1.2	I3C core controller register map.
TCRI recovery specification, version 1.0	I3C core controller recovery interface.
NIST SP 800-90A, revision 1	DRBG and SEP random-number generation.
NIST SP 800-90B	Entropy Source and SEP TRNG entropy assessment and health tests.
FIPS 140-2	Entropy Source discussion of planned certification readiness.
FIPS 203	Adams Bridge ML-KEM-1024 operations.
FIPS 204	Adams Bridge ML-DSA-87 operations and SEP lifecycle signing policy.

4. External Design Documentation

Table 4 identifies the upstream design documentation used by the subsystem chapters.

Table 4. External design documentation references
Document or project	Referenced for
Rocket Core	SMC CPU and memory system.
VeeR EL2 Programmer’s Reference Manual	SEP CPU architecture, CSRs and interrupt behavior.
iDMA	SMC DMA engine.
Caliptra Adams Bridge documentation	SEP post-quantum cryptographic accelerator.
OpenTitan HMAC documentation	SEP HMAC-SHA2 accelerator and programming model.
OpenTitan OTBN documentation	SEP public-key accelerator and programming model.
OpenTitan AES documentation	SEP AES cipher and programming model.
OpenTitan KMAC documentation	SEP KMAC-SHA3 accelerator and programming model.
OpenTitan Key Manager	Background on a comparable key manager design. The OCAH Key Manager firmware interface is defined by its own firmware chapter, not by this document.
OpenTitan CSRNG and EDN	DRBG core register semantics and application entropy delivery.
OpenTitan DMA Controller	SEP DMA and its programming model.
OpenTitan SPI Host documentation	SEP SPI host and programming model.
OpenTitan Always-On Timer documentation	SEP watchdog timer and programming model.
OpenTitan I2C Controller documentation	SMC I2C controller architecture and programming model. The I2C chapter also cites the upstream source.
OpenTitan I2C Device Interface Functions	I2C controller firmware interface.
OpenTitan Cryptolib API	SEP cryptographic software interface background.