Reset

Reset is handled hierarchically so that the management infrastructure comes out of reset first and then releases dependent domains in a controlled order. A global power-on reset (rst_cold_ni) establishes a known state for the entire chiplet, but the always-on domain is intended to be released first so that early control logic is live immediately. From there, the SMC sequences reset deassertion for the SMN and for downstream managed blocks according to platform dependencies, boot policy, and fault conditions. This staged reset model also supports partial and warm-reset behaviours in which application domains can be reset or recovered without fully tearing down the always-on management infrastructure.

The reset hierarchy within the SMU proceeds as follows:

  1. Power-on / cold reset. The external rst_cold_ni is asserted during power-up and deasserted synchronously after supply voltages stabilise. The powergood_i input indicates that supplies are stable.

  2. SMC reset synchronisation. The SMC reset unit (smc_reset_unit) generates domain-specific synchronised resets from the single cold reset input:

    • rst_primary_smc_clk_no — synchronised to the primary SMC clock domain

    • rst_primary_ref_clk_no — synchronised to the reference clock domain

    • rst_primary_periph_clk_no — synchronised to the peripheral clock domain

    • rst_cold_stable_ref_clk_no — stable cold reset in the reference domain

  3. DTP reset. The DTP is held in reset by the SMC’s primary synchronised reset (rst_primary_smc_clk_no). In addition, the JTAG state machine requires a power-on reset that remains asserted until supplies are stable; at the SMU level this is the powergood_stable signal generated by the SMC.

  4. SEP reset. The SEP is held in reset by the same SMC primary reset (rst_primary_smc_clk_no). The SEP watchdog timer also drives a shared warm-reset path (rst_wdt_n at the SMU level); its blast radius is limited to the SEP CPU and the SEP warm scratch registers, plus the parts of the SMC that the SMC reset unit routes through the warm-reset path.

  5. Downstream subsystem sequencing. The SMC sequences reset deassertion for up to 32 managed subsystems through ss_reset_ctrl_o[31:0] and isolation through isolate_req_o[31:0]. Subsystems report completion via ss_reset_complete_i[31:0].

  6. Function Level Reset (FLR). Asserting cfg_flr_pf_active_i triggers a warm reset sequence that isolates subsystems through isolate_req_o and performs controlled reset propagation without tearing down the always-on infrastructure.

  7. Debug reset overrides. The DTP provides JTAG IC_RESET controls that can override the fuse, cold, cool, warm, and per-subsystem reset domains independently for debug scenarios. These are wired through the SMU into the SMC reset unit and the SEP reset controller. The Programmer’s Guide gives the programming order these overrides require.

1. IC_RESET TDR

The primary TAP implements the IEEE 1149.1-2013 §17 IC_RESET TDR as three slices on the scan chain from TDI to TDO, followed by a single reset_hold bit nearest TDO:

  • SMC slice (nearest TDI). Fuse, cold, cool, and warm resets, plus cold and warm resets for each of the 32 managed subsystems. The SMU consumes this slice internally.

  • SEP slice. SEP main reset and the Adams Bridge, TRNG, KMAC, HMAC, AES, OTBN, and Key Manager resets. Present when SEP is instantiated; omitted otherwise. The SMU consumes this slice internally.

  • External slice. Reset overrides for logic outside the SMU. The ports in this slice are adopter-defined: the integrator supplies the slice type and routes the SMU output to that logic. OCAH does not name the external bits. The default type is a single-override stub.

Each port carries an override-enable bit and an active-low reset value. The Integrator Guide records the SMU port map, including how to size the external slice.

For the detailed reset controller design, sequencing FSM, reset register interface, and clock-reset interaction, refer to the Clock and Reset Management chapter:

Clock and Reset Management

For integration-level reset procedures, refer to the Integrator Guide. The Programmer’s Guide lists the resets that software requests in its SMC and SEP reset overviews.