AXI-over-UCIe
Connect the UCIe 3.0 FDI bringup controller to the AXI-over-UCIe protocol engine.
AOU_TOP is the top-level wrapper around AOU_FDI_BRINGUP_CTRL, the UCIe 3.0 FDI state machine, and AOU_CORE_TOP, the AXI-over-UCIe protocol engine. The bringup controller manages the FDI handshakes (wake, clock, state, and rx-active) and drives I_INT_FSM_IN_ACTIVE into the AOU core, so the core needs no external UCIE_CORE connection.
The FDI data-plane ports mirror the _0/_1 naming and the +define+TWO_PHY gating of AOU_CORE_TOP. PHY0 is always present. PHY1 and I_PHY_TYPE are exposed only when the design is built with +define+TWO_PHY.
The single FDI_CONFIG parameter is an integer that picks the FDI data bus widths for both PHYs and, in two-PHY builds, the per-PHY pairing; packet_def_pkg::FDI_CFG_* enumerates its values. FDI_CONFIG is forwarded unchanged to AOU_CORE_TOP. Its default matches the legacy +define+FDI_32B single-PHY configuration. Keeping FDI_CONFIG consistent with +define+TWO_PHY is the integrator's responsibility. The local FDI_IF_WD0 and FDI_IF_WD1 localparams are derived from FDI_CONFIG only to size this wrapper's own FDI ports and the FIFO-depth defaults, and are not forwarded.
The RX W and R FIFO depths default to 140 when either FDI data path is 1024 bits (128B) wide, and to 88 otherwise. This matches the legacy +define+FDI_128B configuration, which applied to both the single-PHY (FDI_IF_WD0 == 1024) and the two-PHY (FDI_IF_WD1 == 1024) cases.
The ports fall into these groups:
- APB slave interface.
- AXI master interface (O_AOU_RX_AXI_M_*, I_AOU_TX_AXI_M_*): the RX side, facing the downstream bus.
- AXI slave interface (I_AOU_TX_AXI_S_*, O_AOU_RX_AXI_S_*): the TX side, facing the upstream bus.
- PHY type select (I_PHY_TYPE), present only with +define+TWO_PHY.
- FDI data path for PHY0, always present, and for PHY1, present only with +define+TWO_PHY.
- FDI bringup control (I_PL_*, O_LP_*), connected to AOU_FDI_BRINGUP_CTRL.
- FDI bringup software control (I_SW_*) and status (O_FDI_FSM_STATE, O_FDI_LINK_UP).
- Interrupt outputs (INT_*).
- Bus quiescence inputs from external transaction monitors.
- DFT.
Parameters
| Name | Type | Default | Description |
|---|---|---|---|
RP_COUNT | | 1 | Number of receive ports (AXI master/slave pairs), up to 4. |
FDI_CONFIG | int | FDI_CFG_SP_32B | FDI configuration, one of packet_def_pkg::FDI_CFG_*. |
FDI_IF_WD0 | int | (FDI_CONFIG == FDI_CFG_SP_32B ) ? 256 : (FDI_CONFIG == FDI_CFG_SP_64B ) ? 512 : (FDI_CONFIG == FDI_CFG_SP_128B ) ? 1024 : (FDI_CONFIG == FDI_CFG_TP_32B_64B ) ? 256 : (FDI_CONFIG == FDI_CFG_TP_64B_128B) ? 512 : 256 | PHY0 FDI data bus width, in bits. Local only. |
FDI_IF_WD1 | int | (FDI_CONFIG == FDI_CFG_SP_32B ) ? 512 : (FDI_CONFIG == FDI_CFG_SP_64B ) ? 512 : (FDI_CONFIG == FDI_CFG_SP_128B ) ? 1024 : (FDI_CONFIG == FDI_CFG_TP_32B_64B ) ? 512 : (FDI_CONFIG == FDI_CFG_TP_64B_128B) ? 1024 : 512 | PHY1 FDI data bus width, in bits. Local only. |
RP0_RX_AW_FIFO_DEPTH | | 44 | RP0 RX write-address FIFO depth. |
RP0_RX_AR_FIFO_DEPTH | | 44 | RP0 RX read-address FIFO depth. |
RP0_RX_W_FIFO_DEPTH | | ((FDI_IF_WD0 == 1024) || (FDI_IF_WD1 == 1024)) ? 140 : 88 | RP0 RX write-data FIFO depth. |
RP0_RX_R_FIFO_DEPTH | | ((FDI_IF_WD0 == 1024) || (FDI_IF_WD1 == 1024)) ? 140 : 88 | RP0 RX read-data FIFO depth. |
RP0_RX_B_FIFO_DEPTH | | 44 | RP0 RX write-response FIFO depth. |
RP1_RX_AW_FIFO_DEPTH | | 44 | RP1 RX write-address FIFO depth. |
RP1_RX_AR_FIFO_DEPTH | | 44 | RP1 RX read-address FIFO depth. |
RP1_RX_W_FIFO_DEPTH | | ((FDI_IF_WD0 == 1024) || (FDI_IF_WD1 == 1024)) ? 140 : 88 | RP1 RX write-data FIFO depth. |
RP1_RX_R_FIFO_DEPTH | | ((FDI_IF_WD0 == 1024) || (FDI_IF_WD1 == 1024)) ? 140 : 88 | RP1 RX read-data FIFO depth. |
RP1_RX_B_FIFO_DEPTH | | 44 | RP1 RX write-response FIFO depth. |
RP2_RX_AW_FIFO_DEPTH | | 44 | RP2 RX write-address FIFO depth. |
RP2_RX_AR_FIFO_DEPTH | | 44 | RP2 RX read-address FIFO depth. |
RP2_RX_W_FIFO_DEPTH | | ((FDI_IF_WD0 == 1024) || (FDI_IF_WD1 == 1024)) ? 140 : 88 | RP2 RX write-data FIFO depth. |
RP2_RX_R_FIFO_DEPTH | | ((FDI_IF_WD0 == 1024) || (FDI_IF_WD1 == 1024)) ? 140 : 88 | RP2 RX read-data FIFO depth. |
RP2_RX_B_FIFO_DEPTH | | 44 | RP2 RX write-response FIFO depth. |
RP3_RX_AW_FIFO_DEPTH | | 44 | RP3 RX write-address FIFO depth. |
RP3_RX_AR_FIFO_DEPTH | | 44 | RP3 RX read-address FIFO depth. |
RP3_RX_W_FIFO_DEPTH | | ((FDI_IF_WD0 == 1024) || (FDI_IF_WD1 == 1024)) ? 140 : 88 | RP3 RX write-data FIFO depth. |
RP3_RX_R_FIFO_DEPTH | | ((FDI_IF_WD0 == 1024) || (FDI_IF_WD1 == 1024)) ? 140 : 88 | RP3 RX read-data FIFO depth. |
RP3_RX_B_FIFO_DEPTH | | 44 | RP3 RX write-response FIFO depth. |
RX_AW_FIFO_RS_EN | | 1 | Register slice on the RX write-address FIFO output. |
RX_AR_FIFO_RS_EN | | 1 | Register slice on the RX read-address FIFO output. |
RX_W_FIFO_RS_EN | | 1 | Register slice on the RX write-data FIFO output. |
RX_R_FIFO_RS_EN | | 1 | Register slice on the RX read-data FIFO output. |
RX_B_FIFO_RS_EN | | 1 | Register slice on the RX write-response FIFO output. |
RP0_AXI_DATA_WD | | 512 | RP0 AXI data width, in bits. |
RP1_AXI_DATA_WD | | 512 | RP1 AXI data width, in bits. |
RP2_AXI_DATA_WD | | 512 | RP2 AXI data width, in bits. |
RP3_AXI_DATA_WD | | 512 | RP3 AXI data width, in bits. |
AXI_PEER_DIE_MAX_DATA_WD | | 1024 | Widest AXI data width on the peer die, in bits. |
APB_ADDR_WD | | 32 | APB address width. |
APB_DATA_WD | | 32 | APB data width. |
S_RD_MO_CNT | | 32 | Outstanding reads on the AXI slave interface. |
S_WR_MO_CNT | | 32 | Outstanding writes on the AXI slave interface. |
M_RD_MO_CNT | | 32 | Outstanding reads on the AXI master interface. |
M_WR_MO_CNT | | 32 | Outstanding writes on the AXI master interface. |
RP_AXI_DATA_WD_MAX | | max4(RP0_AXI_DATA_WD, RP1_AXI_DATA_WD, RP2_AXI_DATA_WD, RP3_AXI_DATA_WD) | Widest RPn AXI data width; sizes the AXI data ports. |
RP_AXI_STRB_WD_MAX | | RP_AXI_DATA_WD_MAX / 8 | AXI write-strobe width for that data width. |
AXI_ADDR_WD | | 64 | AXI address width. |
AXI_ID_WD | | 10 | AXI ID width. |
AXI_LEN_WD | | 8 | AXI burst-length width. |
Ports
| Name | Direction | Type | Description |
|---|---|---|---|
I_CLK | input | logic | Clock for the AOU core and the FDI bringup controller. |
I_RESETN | input | logic | Active-low asynchronous reset for the I_CLK domain. |
I_PCLK | input | logic | APB clock, asynchronous to I_CLK. |
I_PRESETN | input | logic | Active-low reset for the I_PCLK domain. |
I_AOU_APB_SI0_PSEL | input | logic | APB select. |
I_AOU_APB_SI0_PENABLE | input | logic | APB enable. |
I_AOU_APB_SI0_PADDR | input | logic [APB_ADDR_WD-1:0] | APB address. |
I_AOU_APB_SI0_PWRITE | input | logic | APB write. |
I_AOU_APB_SI0_PWDATA | input | logic [APB_DATA_WD-1:0] | APB write data. |
O_AOU_APB_SI0_PRDATA | output | logic [APB_DATA_WD-1:0] | APB read data. |
O_AOU_APB_SI0_PREADY | output | logic | APB ready. |
O_AOU_APB_SI0_PSLVERR | output | logic | APB slave error. |
O_AOU_RX_AXI_M_ARID | output | logic [RP_COUNT-1:0][AXI_ID_WD-1:0] | AXI master read-address ID. |
O_AOU_RX_AXI_M_ARADDR | output | logic [RP_COUNT-1:0][AXI_ADDR_WD-1:0] | AXI master read address. |
O_AOU_RX_AXI_M_ARLEN | output | logic [RP_COUNT-1:0][AXI_LEN_WD-1:0] | AXI master read burst length. |
O_AOU_RX_AXI_M_ARSIZE | output | logic [RP_COUNT-1:0][2:0] | AXI master read transfer size. |
O_AOU_RX_AXI_M_ARBURST | output | logic [RP_COUNT-1:0][1:0] | AXI master read burst type. |
O_AOU_RX_AXI_M_ARLOCK | output | logic [RP_COUNT-1:0] | AXI master read lock. |
O_AOU_RX_AXI_M_ARCACHE | output | logic [RP_COUNT-1:0][3:0] | AXI master read cache attributes. |
O_AOU_RX_AXI_M_ARPROT | output | logic [RP_COUNT-1:0][2:0] | AXI master read protection. |
O_AOU_RX_AXI_M_ARQOS | output | logic [RP_COUNT-1:0][3:0] | AXI master read QoS. |
O_AOU_RX_AXI_M_ARVALID | output | logic [RP_COUNT-1:0] | AXI master read-address valid. |
I_AOU_RX_AXI_M_ARREADY | input | logic [RP_COUNT-1:0] | AXI master read-address ready. |
I_AOU_TX_AXI_M_RID | input | logic [RP_COUNT-1:0][AXI_ID_WD-1:0] | AXI master read-data ID. |
I_AOU_TX_AXI_M_RDATA | input | logic [RP_COUNT-1:0][RP_AXI_DATA_WD_MAX-1:0] | AXI master read data. |
I_AOU_TX_AXI_M_RRESP | input | logic [RP_COUNT-1:0][1:0] | AXI master read response. |
I_AOU_TX_AXI_M_RLAST | input | logic [RP_COUNT-1:0] | AXI master last read beat. |
I_AOU_TX_AXI_M_RVALID | input | logic [RP_COUNT-1:0] | AXI master read-data valid. |
O_AOU_TX_AXI_M_RREADY | output | logic [RP_COUNT-1:0] | AXI master read-data ready. |
O_AOU_RX_AXI_M_AWID | output | logic [RP_COUNT-1:0][AXI_ID_WD-1:0] | AXI master write-address ID. |
O_AOU_RX_AXI_M_AWADDR | output | logic [RP_COUNT-1:0][AXI_ADDR_WD-1:0] | AXI master write address. |
O_AOU_RX_AXI_M_AWLEN | output | logic [RP_COUNT-1:0][AXI_LEN_WD-1:0] | AXI master write burst length. |
O_AOU_RX_AXI_M_AWSIZE | output | logic [RP_COUNT-1:0][2:0] | AXI master write transfer size. |
O_AOU_RX_AXI_M_AWBURST | output | logic [RP_COUNT-1:0][1:0] | AXI master write burst type. |
O_AOU_RX_AXI_M_AWLOCK | output | logic [RP_COUNT-1:0] | AXI master write lock. |
O_AOU_RX_AXI_M_AWCACHE | output | logic [RP_COUNT-1:0][3:0] | AXI master write cache attributes. |
O_AOU_RX_AXI_M_AWPROT | output | logic [RP_COUNT-1:0][2:0] | AXI master write protection. |
O_AOU_RX_AXI_M_AWQOS | output | logic [RP_COUNT-1:0][3:0] | AXI master write QoS. |
O_AOU_RX_AXI_M_AWVALID | output | logic [RP_COUNT-1:0] | AXI master write-address valid. |
I_AOU_RX_AXI_M_AWREADY | input | logic [RP_COUNT-1:0] | AXI master write-address ready. |
O_AOU_RX_AXI_M_WDATA | output | logic [RP_COUNT-1:0][RP_AXI_DATA_WD_MAX-1:0] | AXI master write data. |
O_AOU_RX_AXI_M_WSTRB | output | logic [RP_COUNT-1:0][RP_AXI_STRB_WD_MAX-1:0] | AXI master write strobes. |
O_AOU_RX_AXI_M_WLAST | output | logic [RP_COUNT-1:0] | AXI master last write beat. |
O_AOU_RX_AXI_M_WVALID | output | logic [RP_COUNT-1:0] | AXI master write-data valid. |
I_AOU_RX_AXI_M_WREADY | input | logic [RP_COUNT-1:0] | AXI master write-data ready. |
I_AOU_TX_AXI_M_BID | input | logic [RP_COUNT-1:0][AXI_ID_WD-1:0] | AXI master write-response ID. |
I_AOU_TX_AXI_M_BRESP | input | logic [RP_COUNT-1:0][1:0] | AXI master write response. |
I_AOU_TX_AXI_M_BVALID | input | logic [RP_COUNT-1:0] | AXI master write-response valid. |
O_AOU_TX_AXI_M_BREADY | output | logic [RP_COUNT-1:0] | AXI master write-response ready. |
I_AOU_TX_AXI_S_ARID | input | logic [RP_COUNT-1:0][AXI_ID_WD-1:0] | AXI slave read-address ID. |
I_AOU_TX_AXI_S_ARADDR | input | logic [RP_COUNT-1:0][AXI_ADDR_WD-1:0] | AXI slave read address. |
I_AOU_TX_AXI_S_ARLEN | input | logic [RP_COUNT-1:0][AXI_LEN_WD-1:0] | AXI slave read burst length. |
I_AOU_TX_AXI_S_ARSIZE | input | logic [RP_COUNT-1:0][2:0] | AXI slave read transfer size. |
I_AOU_TX_AXI_S_ARBURST | input | logic [RP_COUNT-1:0][1:0] | AXI slave read burst type. |
I_AOU_TX_AXI_S_ARLOCK | input | logic [RP_COUNT-1:0] | AXI slave read lock. |
I_AOU_TX_AXI_S_ARCACHE | input | logic [RP_COUNT-1:0][3:0] | AXI slave read cache attributes. |
I_AOU_TX_AXI_S_ARPROT | input | logic [RP_COUNT-1:0][2:0] | AXI slave read protection. |
I_AOU_TX_AXI_S_ARQOS | input | logic [RP_COUNT-1:0][3:0] | AXI slave read QoS. |
I_AOU_TX_AXI_S_ARVALID | input | logic [RP_COUNT-1:0] | AXI slave read-address valid. |
O_AOU_TX_AXI_S_ARREADY | output | logic [RP_COUNT-1:0] | AXI slave read-address ready. |
O_AOU_RX_AXI_S_RID | output | logic [RP_COUNT-1:0][AXI_ID_WD-1:0] | AXI slave read-data ID. |
O_AOU_RX_AXI_S_RDATA | output | logic [RP_COUNT-1:0][RP_AXI_DATA_WD_MAX-1:0] | AXI slave read data. |
O_AOU_RX_AXI_S_RRESP | output | logic [RP_COUNT-1:0][1:0] | AXI slave read response. |
O_AOU_RX_AXI_S_RLAST | output | logic [RP_COUNT-1:0] | AXI slave last read beat. |
O_AOU_RX_AXI_S_RVALID | output | logic [RP_COUNT-1:0] | AXI slave read-data valid. |
I_AOU_RX_AXI_S_RREADY | input | logic [RP_COUNT-1:0] | AXI slave read-data ready. |
I_AOU_TX_AXI_S_AWID | input | logic [RP_COUNT-1:0][AXI_ID_WD-1:0] | AXI slave write-address ID. |
I_AOU_TX_AXI_S_AWADDR | input | logic [RP_COUNT-1:0][AXI_ADDR_WD-1:0] | AXI slave write address. |
I_AOU_TX_AXI_S_AWLEN | input | logic [RP_COUNT-1:0][AXI_LEN_WD-1:0] | AXI slave write burst length. |
I_AOU_TX_AXI_S_AWSIZE | input | logic [RP_COUNT-1:0][2:0] | AXI slave write transfer size. |
I_AOU_TX_AXI_S_AWBURST | input | logic [RP_COUNT-1:0][1:0] | AXI slave write burst type. |
I_AOU_TX_AXI_S_AWLOCK | input | logic [RP_COUNT-1:0] | AXI slave write lock. |
I_AOU_TX_AXI_S_AWCACHE | input | logic [RP_COUNT-1:0][3:0] | AXI slave write cache attributes. |
I_AOU_TX_AXI_S_AWPROT | input | logic [RP_COUNT-1:0][2:0] | AXI slave write protection. |
I_AOU_TX_AXI_S_AWQOS | input | logic [RP_COUNT-1:0][3:0] | AXI slave write QoS. |
I_AOU_TX_AXI_S_AWVALID | input | logic [RP_COUNT-1:0] | AXI slave write-address valid. |
O_AOU_TX_AXI_S_AWREADY | output | logic [RP_COUNT-1:0] | AXI slave write-address ready. |
I_AOU_TX_AXI_S_WDATA | input | logic [RP_COUNT-1:0][RP_AXI_DATA_WD_MAX-1:0] | AXI slave write data. |
I_AOU_TX_AXI_S_WSTRB | input | logic [RP_COUNT-1:0][RP_AXI_STRB_WD_MAX-1:0] | AXI slave write strobes. |
I_AOU_TX_AXI_S_WLAST | input | logic [RP_COUNT-1:0] | AXI slave last write beat. |
I_AOU_TX_AXI_S_WVALID | input | logic [RP_COUNT-1:0] | AXI slave write-data valid. |
O_AOU_TX_AXI_S_WREADY | output | logic [RP_COUNT-1:0] | AXI slave write-data ready. |
O_AOU_RX_AXI_S_BID | output | logic [RP_COUNT-1:0][AXI_ID_WD-1:0] | AXI slave write-response ID. |
O_AOU_RX_AXI_S_BRESP | output | logic [RP_COUNT-1:0][1:0] | AXI slave write response. |
O_AOU_RX_AXI_S_BVALID | output | logic [RP_COUNT-1:0] | AXI slave write-response valid. |
I_AOU_RX_AXI_S_BREADY | input | logic [RP_COUNT-1:0] | AXI slave write-response ready. |
I_FDI_PL_0_VALID | input | logic | PHY0 received-flit valid. |
I_FDI_PL_0_DATA | input | logic [FDI_IF_WD0-1:0] | PHY0 received-flit data. |
I_FDI_PL_0_FLIT_CANCEL | input | logic | PHY0 flit cancel. |
I_FDI_PL_0_TRDY | input | logic | PHY0 ready for transmit-flit data. |
I_FDI_PL_0_STALLREQ | input | logic | PHY0 stall request. |
I_FDI_PL_0_STATE_STS | input | logic [3:0] | PHY0 state status. |
O_FDI_LP_0_DATA | output | logic [FDI_IF_WD0-1:0] | PHY0 transmit-flit data. |
O_FDI_LP_0_VALID | output | logic | PHY0 transmit-flit valid. |
O_FDI_LP_0_IRDY | output | logic | PHY0 transmit initiator ready. |
O_FDI_LP_0_STALLACK | output | logic | PHY0 stall acknowledge. |
I_PL_INBAND_PRES | input | logic | PHY in-band presence. |
I_PL_CLK_REQ | input | logic | PHY clock request. |
I_PL_WAKE_ACK | input | logic | PHY wake acknowledge. |
I_PL_RX_ACTIVE_REQ | input | logic | PHY rx-active request. |
O_LP_STATE_REQ | output | logic [3:0] | Link state request to the PHY. |
O_LP_WAKE_REQ | output | logic | Wake request to the PHY. |
O_LP_CLK_ACK | output | logic | Clock acknowledge to the PHY. |
O_LP_RX_ACTIVE_STS | output | logic | Rx-active status to the PHY. |
I_SW_ACTIVATE_START | input | logic | Software request to start activation. |
I_SW_DEACTIVATE_START | input | logic | Software request to start deactivation. |
I_SW_RETRAIN_REQ | input | logic | Software request to retrain the link. |
I_SW_LINKERROR_INJECT | input | logic | Software request to inject a link error. |
O_FDI_FSM_STATE | output | logic [3:0] | FDI bringup FSM state. |
O_FDI_LINK_UP | output | logic | FDI link is up. |
INT_REQ_LINKRESET | output | logic | Link reset request interrupt. |
INT_SI0_ID_MISMATCH | output | logic | AXI slave ID mismatch interrupt. |
INT_MI0_ID_MISMATCH | output | logic | AXI master ID mismatch interrupt. |
INT_EARLY_RESP_ERR | output | logic | Early-response error interrupt. |
INT_ACTIVATE_START | output | logic | Activation start interrupt from the AOU core. Also drives the bringup controller. |
INT_DEACTIVATE_START | output | logic | Deactivation start interrupt from the AOU core. Also drives the bringup controller. |
I_MST_BUS_CLEANY_COMPLETE | input | logic | All responses to remote-die requests have completed. Tie to 1 when BUS_CLEANY is not used. |
I_SLV_BUS_CLEANY_COMPLETE | input | logic | All remote-die responses to local requests have arrived. Tie to 1 when BUS_CLEANY is not used. |
TIEL_DFT_MODESCAN | input | logic | DFT scan mode. Tie low for functional operation. |