List of Figures
Select a figure to open its topic. Figure numbers are local to each HTML topic; the PDF numbers figures consecutively across the book.
AoU Architecture
- Figure 1. Architecture of AOU_CORE
- Figure 2. Block Diagram of Single RP AOU_TX_CORE
- Figure 3. TX_CORE QoS Scheme
- Figure 4. Round-Robin arbitration example
- Figure 5. Port QoS arbitration example
- Figure 6. AXI QoS arbitration example
- Figure 7. Block Diagram of AOU_RX_CORE
- Figure 8. Architecture of Chunk Decoder
- Figure 9. Data FIFO
- Figure 10. Req / Resp FIFO
- Figure 11. AXI4MUX_3X1_TOP
- Figure 12. AoU successful early write response
- Figure 13. AoU error after an early write response
- Figure 14. AoU write-outstanding backpressure
- Figure 15. AoU bufferable then non-bufferable writes
- Figure 16. AoU non-bufferable then bufferable writes
- Figure 17. Write Aggregation -- Narrow-to-Wide Beat Merging
- Figure 18. Block Diagram of AOU_CRD_CTRL
- Figure 19. Example of WDATA and WSTRB FIFO Operation
- Figure 20. Example of RDATA FIFO Operation
- Figure 21. Resource Plane Remapping
- Figure 22. UCIe Flit Cancel - Retransmit case
- Figure 23. UCIe Flit Cancel - Flit Partially Valid case
- Figure 24. UCIe Flit Cancel - Full Flit Cancel case
- Figure 25. Example of selecting valid chunks for RX_CORE
AoU Overview and Features
AoU PPA
Clock Domains
Clocks and Resets
JTAG Operation
Overview
AVSBus Controller
Cross-Trigger Matrix
Cross-Trigger Network
Cross-Trigger Port
Entropy Source
GPIO Peripheral
I2C Controller
JTAG Interface Unit
JTAG PTAP
- Figure 1. PTAP module architecture
- Figure 2. JTAG2AXI single-operation layout
- Figure 3. JTAG2AXI series-control layout
- Figure 4. JTAG2AXI incrementing data layout for effective size 0
- Figure 5. JTAG2AXI incrementing data layout for effective size 1
- Figure 6. JTAG2AXI incrementing data layout for effective size 2
- Figure 7. JTAG2AXI incrementing data layout for effective size 3
- Figure 8. JTAG2AXI non-incrementing data layout for effective size 0
- Figure 9. JTAG2AXI non-incrementing data layout for effective size 1
- Figure 10. JTAG2AXI non-incrementing data layout for effective size 2
- Figure 11. JTAG2AXI non-incrementing data layout for effective size 3
- Figure 12. JTAG2AXI error-status data layout for effective size 0
- Figure 13. JTAG2AXI error-status data layout for effective size 1
- Figure 14. JTAG2AXI error-status data layout for effective size 2
- Figure 15. JTAG2AXI error-status data layout for effective size 3
Key Manager (KM)
SRAM Scrambling
UART 16550
Platform Overview
Adams Bridge (ABR)
Clocks and Resets
Cryptographic Subsystem
Direct Memory Access (DMA)
Interconnect
Life Cycle Controller (LCC)
OTBN PKA Public Key Accelerator
OTP Fuse Controller
Peripheral Subsystem
SEP Reset Controller
Token Processing
TRNG and DRBG
Clocks and Resets
- Figure 1. SMC clock tree and clock domains in u_smc_base
- Figure 2. SMC clock tree and clock domains in u_smc_cpu_wrapper and u_smc_peripherals
- Figure 3. SMC reset unit architecture
- Figure 4. SMC FLR isolation connections between chiplets
- Figure 5. SMC-driven FLR isolation
- Figure 6. Tile-request-driven FLR isolation
- Figure 7. GPIO-driven FLR isolation