System Timer OCTS

A write of 1 to TIMER_START.START starts the primary and loads TIMER_PRESET_HI:LO. The primary then increments by one on each clk_i cycle. It ignores synchronization inputs and generates load and credit pulses for the secondaries.

A secondary loads its own preset when it detects a rising edge on timer_sync_load_i. On each credit edge, it advances its expected count by CTRL.CREDIT_VAL and replaces its actual count with that expected value. Between edges, it increments by CTRL.STEP while credits remain. This replacement is a correction, not just a diagnostic comparison: a secondary count can move backward if its previous increments overshot the boundary.

Choose a nonzero secondary STEP appropriate to the clock ratio. The limit is checked before adding the step, so the last increment can cross it. A lost credit pulse also leaves the expected count behind the primary; receiving a later credit does not recover the missing interval.

CTRL.PULSE_WIDTH sets the high duration in primary clock cycles; zero is treated as one. CREDIT_VAL must exceed this effective width. The FSM accepts triggers only while idle and does not queue them. In particular, START can reload the primary count while an active pulse prevents a new load pulse; use a coordinated reset and setup sequence for restarting.

Each synchronization input passes through an input flop, a two-flop synchronizer and an edge detector in the receiving clock domain. Pulses must stay high long enough to be sampled and low long enough to distinguish successive events. Determine those intervals from the destination clock, routing delay and CDC analysis; the RTL defines no universal frequency ratio, nanosecond timing guarantee or fixed system-wide alignment bound.

STATUS.MODE is 0 for primary and 1 for secondary. STATUS.RUNNING is set when the internal enable is set and the count is nonzero. It can therefore remain set while a secondary is paused for lack of credit, or remain clear immediately after loading a zero preset. It is not a synchronization check.

The secondary core counts cycles spent without credit. Load and credit edges clear this interval counter. The register wrapper retains the largest observed value in CREDIT_EXPIRED; writing any value clears the saved maximum, while only a load or credit pulse clears the running interval counter in the core. Normal credit reception does not clear the saved maximum. In a primary configured from reset, it stays zero.

Use this value to detect waiting for credit, with thresholds derived from the clock ratio and pulse interval. It does not directly measure timestamp error or prove that all credit pulses arrived.

rst_ni asynchronously clears the counter, enable, pulse state and registers. Reset release must meet the integration’s timing requirements; this block does not synchronize reset deassertion internally.

Enable is sticky after a PRIMARY-mode START or a received load edge. There is no stop CSR; writing START=0 does not stop counting. Configure role and timing before starting, and use system reset when a coordinated reconfiguration is needed.

The ports of system_timer_octs are listed in system_timer_octs.

system_timer_octs has no parameters. Its AXI4-Lite request and response types, with 32-bit address and data, are defined in system_timer_octs_pkg.

When operating in PRIMARY mode, the timer generates synchronization pulses: timer_sync_load_o is asserted for CTRL.PULSE_WIDTH cycles when the START register is written, and timer_cnt_credit_o is asserted for CTRL.PULSE_WIDTH cycles every CTRL.CREDIT_VAL cycles. Any synchronization input signals are ignored in PRIMARY mode. In contrast, SECONDARY mode relies on input from the PRIMARY: timer_sync_load_i directs the timer to initialize using a preset value, and timer_cnt_credit_i delivers credit pulses that allow continuous synchronization. In this mode, the outputs remain inactive.

timer_count_o is the live 64-bit count, also readable through TIMER_COUNT_LO and TIMER_COUNT_HI. A PRIMARY advances it by one each clk_i cycle. A SECONDARY advances it by CTRL.STEP each cycle while credits remain.

The RTL defines no setup, hold or clock-to-output limit, maximum clock frequency or frequency ratio between OCTS clock domains. Clock frequency, jitter, reset timing and physical timing constraints must come from the integration timing specification.

Synchronization inputs cross into clk_i as described in Section 2.2; derive the required pulse high and low intervals from the destination clock and CDC analysis. Reset behavior is described in Section 2.4.

The register bank occupies 0x00–0x23 and uses 32-bit AXI4-Lite accesses. Use the enclosing subsystem’s memory map for its base address.