system_timer_octs

Wrap the OCTS system timer with AXI-Lite CSRs and primary/secondary sync.

is_primary_i selects primary versus secondary mode at runtime. timer_sync_load_* and timer_cnt_credit_* carry the OCTS synchronization pulses. timer_count_o is the live 64-bit count; timer_gpio_enable_o gates an optional GPIO export. CREDIT_EXPIRED reads the largest run of credit-starved cycles seen in SECONDARY mode, and a write to it clears the record.

Ports

Table 1. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock. Rising edge; all logic is synchronous to it. Its frequency sets the timer resolution and the synchronization timing.
`rst_ni`	input	`logic`	Async reset, active-low. Assert asynchronously; deassert synchronously to clk_i. Clears all counters, state machines and registers.
`is_primary_i`	input	`logic`	Runtime primary/secondary mode select. 1 selects PRIMARY, which generates the sync pulses; 0 selects SECONDARY, which receives them. Sets the timer behaviour, STATUS.MODE and the direction of the sync signals.
`axil_req_i`	input	`system_timer_octs_axil_req_t`	AXI-Lite CSR request.
`axil_resp_o`	output	`system_timer_octs_axil_resp_t`	AXI-Lite CSR response.
`timer_sync_load_i`	input	`logic`	Inbound sync-load pulse. Active high, synchronized into clk_i and rising-edge detected. Loads the count from the preset and starts the timer. Ignored in PRIMARY mode.
`timer_cnt_credit_i`	input	`logic`	Inbound credit pulse. Active high, synchronized into clk_i and rising-edge detected. Replenishes the credits of a SECONDARY timer. Ignored in PRIMARY mode.
`timer_sync_load_o`	output	`logic`	Outbound sync-load pulse. Active high. The PRIMARY timer pulses it for CTRL.PULSE_WIDTH cycles on a write to START for system-wide initialization. Held low in SECONDARY mode.
`timer_cnt_credit_o`	output	`logic`	Outbound credit pulse. Active high. The PRIMARY timer pulses it every CTRL.CREDIT_VAL cycles, for CTRL.PULSE_WIDTH cycles, to keep the SECONDARY timers synchronized. Held low in SECONDARY mode.
`timer_count_o`	output	`logic [63:0]`	Live 64-bit timer count. Advances by one each cycle in PRIMARY mode and by CTRL.STEP each cycle in SECONDARY mode while credits remain.
`timer_gpio_enable_o`	output	`logic`	TIMER_GPIO_ENABLE.GPIO_ENABLE; enables the GPIO LSIO interface of the timer.
`cur_credits_debug_o`	output	`logic [8:0]`	SECONDARY steps consumed since the last credit or sync pulse.
`credits_left_debug_o`	output	`logic`	High while cur_credits_debug_o is below CTRL.CREDIT_VAL.