Cryptographic Subsystem

The cryptographic accelerators use separate paths for data and secret keys:

The accelerators are derived from OpenTitan, except for the Adams Bridge post-quantum accelerator from Caliptra. The firmware is based on the OpenTitan cryptographic library. Each block’s reference page includes its available register maps; the Detailed Register Map links to those pages.

OCAH adds bus adapters and separate key-delivery paths to the accelerator wrappers. Key Manager writes keys through AXI4-Lite interfaces; the wrappers connect them to the accelerators' key inputs. The following sections describe the shared integration rules and accelerator-specific differences.

Adams Bridge requires 13 SRAM macros with masking enabled (default), or 9 with masking disabled.

Figure 1 shows the accelerator interconnect, Key Manager paths, and external memory interfaces.

In Figure 1, dark lines are host AXI4 and AXI4-Lite paths from the crypto AXI interconnect, and brown lines are the Key Manager private key buses. Each accelerator’s key CSR block is the <accelerator>_wrapper_key_reg block that receives the KEY_SHARE0, KEY_SHARE1 and KEY_CTRL writes described in Section 3 and drives the core’s sideload key port. The Key Manager reaches the key CSR blocks through its internal crossbar; the Adams Bridge key bus leaves on the right, beside the ML-KEM shared-key interrupt that Adams Bridge returns. The host paths to the Key Manager mailbox, the external TRNG registers, the eFuse wrapper and the lifecycle controller are not isolated, and the eFuse and lifecycle legs leave the interconnect as AXI4. All six Key Manager paths, including its eFuse access, pass an isolation stage in sep_crypto_axi_interconnect.

The Key Manager also receives OTP data: the eFuse shadow registers supply the lifecycle state and the identity and class-key fields, and the lifecycle controller supplies the two demotion states. Grey arrows carry entropy, OTP data and status one way; the three entropy streams from the DRBG pass through a source select that can take the external TRNG instead, as the TRNG and DRBG page describes. Grey boxes are outside sep_crypto: the memory macros live in the integration layer, and the entropy pool is u_entropy_fifo in sep. The Adams Bridge SRAMs are 13 macros with masking enabled and 9 without. Interrupts and OpenTitan alerts are not drawn; Table 1 lists them.

The integrator must instantiate the Adams Bridge working SRAMs outside SEP and connect them through the dedicated abr_mem request/response interface. For the memory interface and configuration requirements, see SEP Memory Interfaces in the Integrator Guide.

The sep_crypto module implements the integration layer, with sep_crypto_axi_interconnect centralizing its bus infrastructure. A single 64-bit AXI slave port from the SEP system fabric is decoded to the accelerators and internal peripherals. The host paths to OTBN, HMAC, AES, KMAC, ESRC, CSRNG, and EDN are converted to AXI4-Lite before isolation, with data-width conversion where required by the endpoint. The OpenTitan wrappers then bridge the isolated AXI4-Lite paths to TL-UL.

The Key Manager drives private AXI4-Lite key buses to the accelerator wrappers, which map key words into the sideload structures expected by the OpenTitan cores. These buses are independently isolated so that they drain before either the Key Manager or the destination accelerator enters software reset.

Each accelerator has its own software-controllable reset. The SEP Reset Controller drains and isolates both its host and Key Manager paths before asserting reset; a Key Manager reset similarly drains all of its key paths. The entropy source, CSRNG, and EDN share one coordinated reset. See SEP Reset Controller and Resetting the TRNG.

Figure 2 shows how the resets from the SEP Reset Controller reach the instances inside u_sep_crypto.

Inside u_sep_trng, por_rst_ni resets a 2-flop synchronizer that samples the inverted TRNG reset and drives trng_reset_active. That signal synchronously clears both EDN AXIS adapters and, as trng_entropy_clear_o, the entropy pool. Both adapters take rst_ni. An OTBN, AES or KMAC software reset cancels that engine’s endpoints in the crypto adapter (see SEP Reset Controller). The Key Manager conditions sep_reset_n into its cold domain through u_cold_rst_sync, and the gated Key Manager reset or its software reset soft_rst_n into a warm reset held for at least 10 cycles, as Key Manager cold and warm reset conditioning shows in more detail.