Telemetry Receiver

Eight little-endian ATB beats form a 64-bit packet. One or more packets form a message that ends when last_packet is set.

Table 1 defines the fields carried in each telemetry packet.

A counter is valid only when all four of its blocks are valid. The number of counters per message is parameterized (default 4); the field layout is fixed.

An accepted beat (atvalid_i && atready_o) writes one assembly byte. Eight beats form a packet, least-significant byte first. Bit 63 marks the last packet; the first packet carries the probe ID at bits [60:56]. Counter decoding starts at block 1 of the first packet, continues across packet boundaries, and assembles each counter most-significant byte first. All four block-valid bits must be set for a counter to be valid; otherwise its decoded value is zero.

The assembly capacity is derived from MAX_NUM_COUNTERS_PER_MESSAGE. Reaching that capacity without a last-packet marker raises MISSING_LAST and resets the write pointer. A last-packet marker also resets the pointer and queues the decoded message. The core accepts beats except during a receiver-flush pulse; message-queue fullness does not apply backpressure.

The queue exposes its oldest message in TELEMETRY_PROBE_ID, TELEMETRY_COUNTER_VLDS and TELEMETRY_COUNTER[0..31]. Reads do not consume data; CTRL.BUFFER_POP advances the queue only when it is nonempty. Empty-queue reads return zero. Counter registers beyond the configured counter count also return zero and have cleared validity bits.

On arrival while full, hardware drops the oldest message and advances the read pointer. There is no snapshot across the separate software reads: overflow can change the visible message mid-read. Arrange sufficient buffering/service rate, or quiesce the producer, when a coherent software snapshot is required. STATUS reports empty/full, not a numeric occupancy count or an overflow interrupt.

irq_o is the OR of the two status sources masked by their corresponding INTR_ENABLE bits. Masking an interrupt does not acknowledge its source.

Reset clears assembly bytes, queue pointers and control/interrupt registers. Queue payload storage is not reset, but empty-queue reads return zero. Supply rst_ni with asynchronous assertion and deassertion synchronized to clk_i.

CTRL.TELEMETRY_RX_FLUSH is a pulse that discards queued messages and resets the assembly pointer. It does not erase either payload store or purge the wrapper’s upstream ATB crossing FIFO. Quiesce traffic when an empty receiver must remain empty after the pulse.

CTRL.TELEMETRY_TX_FLUSH requests a flush from the upstream transmitter through afvalid_o. Hardware clears the request after afvalid_o && afready_i. Completion depends on the producer’s acknowledgement; this is separate from a local receiver flush.

The parameters and ports of telemetry_receiver are listed in telemetry_receiver.

The core has two elaboration parameters. BUFFER_DEPTH (default 8) sets the number of decoded messages the queue holds; it must be a power of two and at least 2. MAX_NUM_COUNTERS_PER_MESSAGE (default 4) sets the number of counters decoded from each message.

The ATB beat width (8 bits), packet width (64 bits), counter width (32 bits) and ATB ID width (7 bits) are package constants. The core register port has an 8-bit address and 32-bit data path.

The global interface provides fundamental clock and reset signals required for basic operation.

clk_i is the core clock and rst_ni its asynchronous, active-low reset; telemetry_receiver_wrap adds clk_telemetry_i / rst_telemetry_ni for the ATB side. Clock frequency, jitter, reset duration and physical timing constraints must come from the integration timing specification.

The ATB (Advanced Trace Bus) interface receives telemetry data using standard ATB protocol.

The interrupt interface provides a single interrupt output for event notification.

telemetry_receiver_wrap defaults to three receivers. It configures their queue depth with TELEMETRY_RECEIVER_BUFFER_DEPTH (default 8) and counter counts with TELEMETRY_RECEIVER_MAX_NUM_COUNTERS_PER_MESSAGE (default 4 per receiver). Actual subsystem values and aperture assignments come from the integration.

The wrapper receives ATB traffic on clk_telemetry_i / rst_telemetry_ni and crosses it into clk_i / rst_ni through an eight-entry asynchronous FIFO per receiver. Its external ready signal reflects crossing-FIFO capacity. This does not turn the core’s decoded-message queue into a lossless backpressured queue. The wrapper also contains flush-handshake synchronizers and returns a decode error for register addresses outside its configured receiver apertures.

Each core occupies 256 bytes with 32-bit registers at four-byte offsets. Control, status, interrupt and message-header registers occupy 0x00–0x18; 32 counter registers occupy 0x80–0xFC. The wrapper map places each receiver in its integration-defined aperture. Reset values and field access types are specified below; reset and flush storage behavior is described in Architecture.