telemetry_receiver

Assemble ATB telemetry packets into buffered counter messages for AXI-Lite readout.

ATB beats accepted on atvalid_i and atready_o fill an assembly buffer; a packet whose last_packet bit is set completes a message, which is decoded into a probe ID and counters and pushed into a BUFFER_DEPTH message FIFO read through the CSRs. A push into a full FIFO drops the oldest message. BUFFER_DEPTH must be a power of two and greater than or equal to 2. CTRL.TELEMETRY_RX_FLUSH empties both buffers and deasserts atready_o, and CTRL.TELEMETRY_TX_FLUSH drives the AF flush request.

debug_o bits:

  • debug_o[0] missing_last_event: assembly buffer filled without last_packet marker.
  • debug_o[1] message_buffer_full: a further push drops the oldest message.
  • debug_o[2] message_buffer_empty.
  • debug_o[3] assembly_buffer_full: the beat being accepted fills the assembly buffer.

Parameters

Table 1. Parameters
NameTypeDefaultDescription
BUFFER_DEPTHint unsigned8Completed-message FIFO depth; must be a power of two and >= 2.
MAX_NUM_COUNTERS_PER_MESSAGEint unsigned4Counters allowed per message; only the first NumCounterRegs are readable.
MaxNumBlocksPerMessageint unsigned1 + (TelemetryCounterWidth / TelemetryDataWidth) * MAX_NUM_COUNTERS_PER_MESSAGEPacket blocks spanning one message: one header block plus one block per counter byte.
MaxNumPacketsPerMessageint unsignedMaxNumBlocksPerMessage % NumBlocksPerPacket == 0 ? MaxNumBlocksPerMessage / NumBlocksPerPacket : MaxNumBlocksPerMessage / NumBlocksPerPacket + 1ATB packets spanning one message.
PacketIndexWidthint unsigned$clog2(MaxNumPacketsPerMessage)Packet-index counter width.
BlockIndexWidthint unsigned$clog2(NumBlocksPerPacket)Block-index counter width.
AssemblyBufferDepthint unsigned(TelemetryPacketWidth / TelemetryDataWidth) * MaxNumPacketsPerMessageAssembly-buffer depth in beats.
AssemblyBufferPtrWidthint unsigned$clog2(AssemblyBufferDepth)Assembly-buffer pointer width.
MessageBufferPtrWidthint unsigned$clog2(BUFFER_DEPTH) + 1Message-FIFO pointer width.

Ports

Table 2. Ports
NameDirectionTypeDescription
clk_iinputlogicSystem clock. All synchronous logic uses the rising edge.
rst_niinputlogicAsync reset, active-low. Assert asynchronously; deassert synchronously to clk_i.
axil_req_iinputaxil_req_tAXI-Lite CSR request.
axil_resp_ooutputaxil_resp_tAXI-Lite CSR response.
atdata_iinputtelemetry_data_tATB data. One 8-bit data beat per transfer.
atid_iinputatb_id_tATB ID. Identifies the trace source. Unused.
atready_ooutputlogicATB ready. High when the receiver can accept a beat; low only while CTRL.TELEMETRY_RX_FLUSH is set.
atvalid_iinputlogicATB valid. High when atdata_i and atid_i are valid.
afvalid_ooutputlogicATB flush valid. Requests a flush from the source. It is CTRL.TELEMETRY_TX_FLUSH, held until afready_i completes the handshake.
afready_iinputlogicATB flush ready. Acknowledges the flush request and clears CTRL.TELEMETRY_TX_FLUSH.
irq_ooutputlogicReceiver interrupt. Active high, level. Asserted while INTR_STATUS.MISSING_LAST is set, or while the FIFO fill level exceeds CTRL.BUFFER_THRESHOLD, each gated by its INTR_ENABLE bit.
debug_ooutputlogic [3:0][0] missing_last_event; [1] message_buffer_full; [2] message_buffer_empty; [3] assembly_buffer_full.