AXI-over-UCIe Bridge (AoU)

The AXI-over-UCIe bridge transports AXI transactions between chiplets through the UCIe interface. These pages reproduce the AOU_CORE Microarchitecture Specification, originally authored by BOS Semiconductors, and follow the AXI over UCIe protocol specification.

Overview and Features — bridge operation, supported interfaces, configurations, and capabilities.

Architecture — transmit and receive paths, width conversion, transaction handling, credits, and UCIe flow control.

Interrupts and Errors — interrupt sources, status reporting, and error handling.

PPA — performance, power, and area.

Appendix B. Referenced Documents — reference list.

Integration details are in the Integrator Guide. Register programming, activation and deactivation flows, and the debug features are in the AoU Programming Guide chapter of the Programmer’s Guide.