AoU Architecture

Figure 3 shows the arbitration path used to select among resource-plane requests.

When multiple RP requests are issued from the TX core, a QoS scheme is applied. The TX core supports three QoS schemes: Round-Robin, Port QoS, and AXI QoS, selected by PRIOR_RP_AXI.ARB_MODE. Each transaction has one of three QoS levels: High, Normal, Low.

The scheme arbitrates the AW and AR channels between RPs. W data is sent in the order of the granted AWs, and B and R responses are arbitrated round-robin whatever the scheme. The arbitration SFRs (PRIOR_RP_AXI and PRIOR_TIMER) are intended to be programmed before the link is activated. They may be written in mission mode, but the arbitration of requests already accepted or in flight is then not guaranteed.

Round-Robin (ARB_MODE = 2'b00) : Round-robin arbitration between valid RP. When a handshake occurs, the RP that will receive the next grant is determined. ARB_MODE = 2'b11 is reserved and behaves as Round-Robin.

Figure 4 illustrates grant rotation among valid resource-plane requests.

Port QoS (ARB_MODE = 2'b01): For each RP, the QoS level is configured by an SFR. Arbitration is performed based on the QoS value in the SFR. The AXI QoS field is not used for arbitration.

The port QoS is divided into three levels: High, Normal, and Low priority. Port QoS can be configured by setting PRIOR_RP_AXI.RPx_PRIOR. A 2-bit field is used for QoS: 3 is High, 2 is Normal and 1 is Low. If the field is set to 0, it is treated as 1 (Low). At reset RP0 and RP1 are Low, RP2 is Normal and RP3 is High.

By default, arbitration is performed in the order High → Normal → Low. If a timeout occurs while a request is at Normal or Low priority, the request is promoted and treated as High priority. The timeout is configured by PRIOR_TIMER (see starvation-prevention timer).

If multiple RPs have the same priority, arbitration among them is performed in a round-robin manner.

Figure 5 illustrates arbitration using the configured resource-plane priorities.

AXI QoS (ARB_MODE = 2'b10): For each RP, the QoS level is determined by the value of the AXI QoS field. Arbitration is performed based on the AXI QoS value. For the 4-bit AXI QoS field, the High and Normal boundaries are the SFR fields AXI_QOS_TO_HP and AXI_QOS_TO_NP. The classifier tests AXI_QOS_TO_HP first: a QoS value at or above AXI_QOS_TO_HP is High. Otherwise a value at or above AXI_QOS_TO_NP is Normal, and a value below AXI_QOS_TO_NP is Low. AXI_QOS_TO_HP must be greater than AXI_QOS_TO_NP. If it is not, the Normal tier is empty: every value at or above AXI_QOS_TO_HP is High, including values that are also at or above AXI_QOS_TO_NP, and every value below AXI_QOS_TO_HP is Low. The reset pair is High 0xA and Normal 0x5, so QoS 10–15 is High, 5–9 is Normal, and 0–4 is Low. By default, arbitration is performed in the order High → Normal → Low. If a timeout occurs while a request is at Normal or Low priority, the request is promoted and treated as High priority (see starvation-prevention timer). If multiple RPs have the same priority, arbitration among them is performed in a round-robin manner.

Figure 6 illustrates arbitration using the AXI QoS fields.

Starvation-prevention timer (Port QoS and AXI QoS): PRIOR_TIMER bounds how long a Normal or Low request can wait behind higher-priority traffic. Each RP has one TX request buffer for AW and one for AR. Each buffer has a 16-bit prescaler that advances every clock cycle while the buffer holds at least one request, holds its count while the buffer is empty, and ticks when it reaches PRIOR_TIMER.TIMER_RESOLUTION, that is once every TIMER_RESOLUTION + 1 cycles. TIMER_RESOLUTION = 0 ticks every cycle; 0xFFFF ticks every 65536 cycles.

Every Normal or Low request in the buffer counts ticks from the cycle it is accepted, not from the time it reaches the head of its buffer. When its count reaches PRIOR_TIMER.TIMER_THRESHOLD, the request is arbitrated as High; the count saturates at TIMER_THRESHOLD. The prescaler is shared by all requests in a buffer and is not restarted when a request arrives, so the first tick a request sees comes 1 to TIMER_RESOLUTION + 1 cycles after acceptance. TIMER_THRESHOLD = 0 promotes every Normal and Low request at once, so all requests arbitrate as High and the result is round-robin. At the reset values (TIMER_RESOLUTION = TIMER_THRESHOLD = 0xF) a request is promoted about 225 to 240 cycles after acceptance.

The timer runs in the Round-Robin scheme too but has no effect there.

According to the AoU specification, even if the data width differs between chips, they must be able to transmit AXI transfers to each other. Because the remote die may issue read or write transactions with data widths of 256, 512, or 1024 bits, the local die is responsible for converting the data to align with its own bus data width. The response must then be reformatted to match the original request size before being returned.

Within AOU_CORE_TOP, the AOU_AXI4MUX_3X1_TOP module performs this function. Figure 11 shows how the structure of the Bypass, AXI Downsizer, and AXI Upsizer varies depending on the AXI data width of the local die.

Three slave channel slots correspond to three possible remote data widths: 256 bits, 512 bits, and 1024 bits. Which slot uses an upsizer, bypass, or downsizer depends on the local die's AXI_DATA_WD parameter. A dedicated variant of the width-adapter module is instantiated for each supported local width:

Table 1 identifies the width-adapter variant and conversion path for each local and remote data width.

Write path routing: The DLEN field embedded in the Write Data message indicates the original data width. AOU_AXI4MUX_3X1_TOP uses this field to steer write data and strobes to the correct channel slot (and therefore through the correct width adapter).

Read path routing: The ARSIZE field of the Read Request message determines which channel slot handles the read response. The 3:1 mux selects the active slave R channel based on a 2-bit selector derived from ARSIZE.

The upsizer (AOU_AXI_UP) packs multiple narrow beats into a single wider beat, recalculating AWLEN/ARLEN accordingly. The downsizer (AOU_AXI_DOWN) splits a single wide beat into multiple narrower beats. Both modules regenerate WLAST internally using a beat counter that compares the current W beat count against the recalculated burst length.

The AoU Write Data message does not carry a WLAST signal. The AOU_AXI_WLAST_GEN module regenerates WLAST by aligning the phases of WriteReq and Write Data messages. It operates upstream of the width adapters in the RX-to-AXI path within AOU_CORE_RP.

The module uses I_S_WDLENGTH (derived from the DLEN field) to determine the number of W beats expected for each AW transaction:

In addition to AOU_AXI_WLAST_GEN, the upsizer and downsizer modules (AOU_AXI_UP and AOU_AXI_DOWN) each contain their own WLAST generation logic to account for the changed burst length after width conversion.

In the AoU specification, the AXI LEN field is fixed at 8 bits, allowing the remote die to issue burst transactions up to the maximum supported by an 8-bit AXI LEN. However, because the local die's bus may not support the full 8-bit burst length, inbound AXI transactions must be split into bursts that the local bus can handle and then reassembled to match the original request.

Even if the burst length increases as a result of data-width conversion, the AXI transactions are always split to ensure they do not exceed the maximum burst length supported by the local bus.

The splitter (AOU_AXI_SPLIT_TR) sits between the 3:1 arbitration mux and the AXI Aggregator inside AOU_AXI4MUX_3X1_TOP. One instance exists per RP, and the maximum burst length can be configured independently for each RP through the AOU_SPLIT_TR_RPn SFRs.

The splitter uses internal address-generator submodules (aou_axi_split_addrgen_ar for reads, aou_axi_split_addrgen_aw for writes) to decompose a single long burst into multiple sub-bursts, each no longer than MAX_AxBURSTLEN + 1 beats. Addresses for each sub-burst are computed from the original base address, burst type, and size.

The address generators recompute address bits [11:0] of each sub-burst; bits [ADDR_WD-1:12] are carried unchanged from the original request. This relies on the request not crossing a 4 KB boundary, which AXI4 guarantees (IHI 0022, A3.4.1). The splitter does not detect a request that crosses one; see Assumptions.

The MAX_AxBURSTLEN value must be of the form 2^n - 1. Legal values are:

Table 2 lists the supported maximum burst-length settings and resulting beat counts.

ID width: The 3:1 mux in front of the splitter appends 2 bits to the AXI ID that name the width path a request took (upsizer, direct or downsizer), so that its responses return to the right path. The splitter carries them and strips them from the manager-side ID, which is therefore ID_WD - 2 bits wide. The sub-bursts of one request share one manager-side ID; their responses return in order, as AXI requires for one ID, and the pending-ID table counts them. The sub-bursts of a request are issued back to back, and nothing limits how many of them are outstanding other than the manager port’s readiness.

Outstanding requests: The pending-ID tables (AOU_SPLIT_RD_PENDING_INFO, AOU_SPLIT_WR_PENDING_INFO) hold one entry per request, not per sub-burst, and are sized by M_RD_MO_CNT / M_WR_MO_CNT (default 32). An RP therefore keeps at most that many remote requests in service, while its manager port may have up to M_RD_MO_CNT x ceil(beats / (MAX_ARBURSTLEN + 1)) read bursts (and likewise writes) outstanding, with beats the request’s length at the manager port’s data width. See AXI ID Mismatch Error for the back-pressure when a table is full.

Read path: The aou_split_tr_arch reorder buffer tracks the sub-burst sequence for each outstanding read. Slave-side RLAST is asserted only when the final beat of the last sub-burst is received, reconstructing the original burst boundary. Intermediate RLAST signals from the master side are consumed internally.

Write path: B responses from sub-bursts are merged. The request’s pending-ID table entry (AOU_SPLIT_WR_PENDING_INFO) counts the sub-bursts still to be answered, and the splitter returns a single B response to the slave side once all sub-bursts have completed. If any sub-burst returns an error (|I_M_BRESP_RS), the merged BRESP_ERR flag is set, propagating the error to the slave-side response.

ID mismatch detection: The splitter exports DEST_TABLE_RID_ERR and DEST_TABLE_BID_ERR signals that flag responses with IDs not matching any outstanding transaction. These feed the INT_MI0_ID_MISMATCH interrupt source via AOU_AXI4MUX_3X1_TOP.

Table 3 identifies the SFR fields associated with burst splitting.

These SFRs must be configured before activation and must not be changed during normal operation.

The SFR enforces the 2^n - 1 constraint in hardware. A write of any value other than 0, 1, 3, 7, 15, 31, 63, 127, or 255 to MAX_AWBURSTLEN or MAX_ARBURSTLEN is stored as 0xF (16 beats, the reset value). Software can confirm the accepted value by reading the field back.

The AOU_EARLY_BRESP_CTRL_AWCACHE module sits between the local AXI subordinate interface and the AOU TX datapath. One instance exists per RP and can be independently enabled or disabled via the per-RP WRITE_EARLY_RESPONSE_RPn.EARLY_BRESP_EN SFR.

When enabled, the module returns an early B response (BRESP = OKAY) to the local AXI manager as soon as both the write address (AW) and the last write data beat (W with WLAST) have been received at the AXI subordinate port -- before the write is packed into AoU messages, transmitted over FDI, and completed on the remote die. This reduces the write latency seen by the local requester at the cost of deferred error reporting.

Early response applies only to bufferable writes (AWCACHE[0] = 1), or to every write when WRITE_EARLY_RESPONSE_RPn.EARLY_ALWAYS_EN is set: the controller treats a write as bufferable when AWCACHE[0] = 1 or EARLY_ALWAYS_EN = 1. Writes that are not bufferable by this definition pass through the module unchanged: the AW, W, and B channels are forwarded directly between the local AXI interface and the AOU TX datapath with no early response generated, and the actual BRESP from the remote die is returned to the local AXI manager as normal. Exclusive writes (AWLOCK = 1) are never answered early, whatever AWCACHE[0] and EARLY_ALWAYS_EN say: only the remote subordinate can decide between EXOKAY and OKAY, so an exclusive write always passes through and returns the remote die’s actual BRESP.

Figure 12 shows the message flow for a bufferable write when the remote die returns a successful response.

When the actual B response arrives from the remote die for a transaction that already received an early response, the controller consumes it internally: O_AXI_S_BVALID is held low (the local AXI manager sees no second response) while O_AXI_M_BREADY is asserted high (the response is drained from the AOU RX path).

If the actual B response from the remote die carries an error (BRESP[1] = 1, indicating SLVERR or DECERR), the error cannot be reported via the AXI B channel because the early OKAY response was already returned to the local AXI manager. Instead, the error is reported via interrupt and SFR capture.

Figure 13 shows how a remote write error is consumed after the local manager has received an early response.

The interrupt fires when the consumed response has BRESP[1] = 1. SW must:

The AOU_EARLY_TABLE inside the controller maintains a tracking table with WR_MO_CNT entries (matching the subordinate write outstanding count). Each entry records:

Table 4 defines the fields tracked for each outstanding write.

The early_go flag ensures that for transactions sharing the same AXI ID, early responses are issued strictly in order. A later bufferable transaction with the same ID waits until all prior same-ID transactions have been responded to (either via early response or actual remote BRESP). This preserves AXI ID ordering even when bufferable and non-bufferable writes with the same ID are interleaved.

The backpressure mechanism described in this section is only active when the early response feature is enabled (EARLY_BRESP_EN = 1). When disabled, the module is a pass-through: AW, W, and B signals are wired directly between the subordinate and manager interfaces with no outstanding-count gating, and write depth is bounded only by whatever the downstream AOU TX datapath can accept. The one ordering rule the pass-through keeps is that W data is accepted only for a write whose AW has been accepted (or is accepted in the same cycle): WREADY stays low toward a manager that presents a W burst ahead of its AW until the AW arrives (AXI4 A3.3.1 allows a subordinate to wait for AWVALID before asserting WREADY).

When enabled, the early table has WR_MO_CNT entries (default 32, set by the S_WR_MO_CNT parameter). Every write that enters the controller -- bufferable or non-bufferable -- occupies one table entry from the time WLAST is accepted until the actual B response arrives from the remote die and is consumed.

Issuing an early B does not free the table entry. The entry remains occupied (pending = 1, out = 1) until the real remote B is received. The table depth therefore limits the total number of writes in flight across the FDI link, not just the number awaiting early response.

When r_aw_cnt == WR_MO_CNT, AWREADY and WREADY are deasserted toward the local AXI manager, stalling both the AW and W channels. The AOU TX datapath and FDI link continue operating normally during this time -- only new write acceptance is blocked. As actual B responses arrive from the remote die and table entries are freed, AWREADY and WREADY reassert and the manager may resume issuing writes.

The pending counter r_aw_cnt is PENDING_CNT_WD (10) bits wide and counts every accepted AW until its actual B is consumed, whether or not early response is enabled; the WR_MO_CNT gating above applies only while it is enabled.

A write-transaction watchdog (AOU_WRITE_TRANS_WDT, one per RP inside the controller) serves as the diagnostic for system-hang detection. When WRITE_EARLY_RESPONSE_RPn.WDT_EN = 1, it counts I_CLK cycles in which the RP has writes outstanding (r_aw_cnt != 0) and neither an AW nor a B handshake occurs; either handshake restarts the count. When the count reaches WRITE_EARLY_RESPONSE_WDT_CTL.WDT_THRESHOLD (shared by all RPs, reset 0xC3500 = 800000 cycles) the sticky status bit WRITE_EARLY_RESPONSE_RPn.WDT_TRANS_TIMEOUT_ERR is set and the INT_EARLY_WDT_ERR interrupt is raised unless masked by AOU_INTERRUPT_MASK.INT_EARLY_WDT_MASK. Software clears the status bit (W1C); the count restarts only on a handshake, so a hung remote die keeps the bit set. See Interrupt.

Figure 14 shows the write queue filling, stalling, and draining as tracking entries become available.

When a bufferable write (TXN0) is followed by a non-bufferable write (TXN1) on the same AWID, the controller handles them as follows:

The local AXI manager sees: early B for TXN0 first, then actual B for TXN1 -- correct AXI ID ordering is preserved.

Figure 15 shows response ordering when a bufferable write precedes a non-bufferable write on the same AXI ID.

When a non-bufferable write (TXN0) is followed by a bufferable write (TXN1) on the same AWID, the early response for TXN1 is delayed until TXN0's actual B has been received.

This is the key latency impact of mixed-cacheability ordering: the bufferable write's early response is delayed until the preceding non-bufferable same-ID write fully completes its round trip through the remote die. The early-response latency benefit is lost for that transaction. Software or interconnect designers should be aware that interleaving non-bufferable writes ahead of bufferable writes on the same ID negates the early-response advantage for those bufferable transactions.

Figure 16 shows response ordering when a non-bufferable write precedes a bufferable write on the same AXI ID.

The EARLY_BRESP_EN SFR may be written at any time, but the internal enable (r_early_bresp_en) only transitions when it is safe to do so:

The same rule applies to EARLY_ALWAYS_EN: change it only while WRITE_RESP_DONE = 1, since the bufferable flag is sampled when the AW is accepted.

Deactivation interaction. AOU_INIT.SLV_TR_COMPLETE is asserted only when, on every RP, no subordinate-side read or write is pending and WRITE_RESP_DONE = 1. Deactivation therefore waits for the actual B responses of early-responded writes, not only for the responses the local AXI manager has seen. See Activation & Deactivation Flow.

The WRITE_EARLY_RESPONSE_RPn register (one per RP: RP0 at 0x0028, RP1 at 0x0040, RP2 at 0x0058, RP3 at 0x0070) contains:

Table 5 defines the per-resource-plane early-response controls.

The WRITE_EARLY_RESPONSE_WDT_CTL register (0x0080, shared by all RPs) contains:

See the full register map for the complete SFR listing.

The AXI Aggregator (AOU_AGGREGATOR) combines narrow read and write data into full-width bus beats to improve bus utilization. It sits downstream of the AXI Transaction Splitter and is the last processing stage before the AXI manager port inside AOU_AXI4MUX_3X1_TOP. One instance exists per RP.

When enabled, the aggregator promotes AWSIZE/ARSIZE to the full bus width and recalculates AWLEN/ARLEN accordingly. For example, an incoming AR with size 256 bits and burst length 16 is converted to size 1024 bits and burst length 4, then issued on the AXI manager interface. When R data returns, it is split to restore the original format. The same principle applies to writes.

When disabled via the per-RP AOU_CON0.RPn_AXI_AGGREGATOR_EN SFR, all master-side signals bypass the aggregator entirely and flow directly to the AXI manager port without modification.

Write aggregation is activated when all of the following conditions are met:

When activated, the aggregator:

A synchronous FIFO of RPn_AGG_WCH_FIFO_DEPTH entries (default 16; it must exceed the longest write burst the local bus issues) decouples the AW and W channels. The AW is issued on the master side only after confirming that sufficient W FIFO space is available for the recalculated AWLEN, preventing deadlocks when the downstream bus back-pressures the W channel.

Figure 17 shows narrow write beats merging into a wider downstream transfer.

Read aggregation follows the same size-promotion logic as writes. ARSIZE and ARLEN are promoted to the full bus width, and ARBURST is passed through (the aggregator does not restrict burst type to INCR). Unlike the write side, read aggregation is not gated on ARCACHE[1] or ARLOCK; non-modifiable and exclusive reads are promoted like any other read.

The AOU_AGGREGATOR_INFO submodule tracks outstanding AR transactions. For each issued AR, it records the original burst geometry (size, length) so that when wide R data returns from the manager side, the module can regenerate the correct slave-side RLAST at the original burst boundaries. Wide R beats are presented to the slave side multiple times (once per original narrow beat) with the appropriate byte-lane selection and the wide beat’s RRESP on each; a failing wide beat therefore pushes one error debug FIFO entry per narrow beat.

Table 7 identifies the resource-plane aggregation enables.

These fields must be configured before activation and must not be changed during normal operation.

The Resource Plane (RP) operates based on the smaller RP count between the local and remote dies and follows a strict one-to-one mapping. RP assignments are configured through the DEST_RP SFR. The values of RP3_DEST, RP2_DEST, RP1_DEST, and RP0_DEST must be unique, and for any RP that is utilized, the configuration on the local and remote dies must be symmetrical.

This configuration must remain static and must be programmed before activation. It must not be altered during normal operation.

When the local and remote dies have different RP_COUNT values, the effective RP count is the smaller of the two. Unused RP slots in the DEST_RP register are functionally don't-care but should be set to non-overlapping values for clean credit routing (see AOU Misconfiguration Behaviour).

Figure 21 shows how resource-plane identifiers are remapped across the link.

For AXI messages (WriteReq, WriteData, ReadReq), the TX path (AOU_TX_AXI_BUFFER) embeds the DEST_RP field from the SFR into the destination RP field of every outgoing message header. The remote die uses this field to route the received message to the correct RP for processing.

For credit grant messages, AOU_TX_CRD_CTRL encodes the local RP index (not the DEST_RP value) so that the remote die can route returned credits to the correct local RP's credit counter. This asymmetry -- destination RP in data messages, source RP in credit messages -- is fundamental to the RP remapping scheme.

No hardware duplicate-detection logic exists for the DEST_RP register. If DEST_RP values are configured with overlapping (duplicate) entries, the credit routing logic in AOU_TX_CRD_CTRL -- which uses a unique case statement on I_RP_DEST_RP[i] -- will fall through to the default case, mapping to the RP0 credit view. This results in silent credit accounting errors rather than a flagged interrupt or error condition.

Software is responsible for ensuring uniqueness and symmetry of the DEST_RP configuration on both link partners before initiating activation.

The AOU_RX_FDI_IF module uses the FDI pl_valid and pl_flit_cancel signals to determine how to handle each incoming chunk. Three cases are distinguished:

Table 11 maps the valid and cancel signals to the receive action.

The AOU_RX_FDI_IF module maintains a staging buffer (r_data) that is HF_PHASE_CNT entries deep, where HF_PHASE_CNT = PHASE_CNT / 2. For the default 512-bit FDI data width, PHASE_CNT = 4 and HF_PHASE_CNT = 2, so the staging buffer holds 2 chunk entries -- one half-flit of data.

A parallel valid array (r_data_valid) tracks which staging buffer entries contain valid chunk data. The output to RX_CORE is gated:

This ensures that chunk presentation is suppressed whenever pl_flit_cancel is asserted, even if valid data exists in the staging buffer. Downstream, AOU_RX_CORE advances its phase counter (r_aou_rx_phase) only when rx_chunk_data_valid is high, so cancel-suppressed cycles stall the RX phase progression without data loss.

Cancel handling is purely combinational on the same clock edge as the FDI input signals. No additional pipeline stages are introduced beyond the 2-entry staging buffer and the phase FSM. The latency from FDI input to valid chunk presentation at RX_CORE is therefore determined solely by the half-flit fill time under normal operation.

The figures below illustrate an example of how only valid chunk data is delivered to RX_CORE. Within the design, pl_data, pl_valid, and pl_flit_cancel are defined as part of the FDI interface. In contrast, rx_chunk_data and rx_chunk_data_valid represent the signals responsible for delivering valid chunks to RX_CORE.

Figure 25 shows the selection of valid chunks for RX_CORE.