Cross-Trigger Network

The CTN supports from 1 to 32 external CTPs, set by its NUM_CTP parameter, which defaults to 16. Each external CTP uses one GPIO pad in wire-OR mode and two or four in point-to-point mode. These ports support both point-to-point and wire-OR cross trigger signaling modes.

Each CTP connects to four separate I/O pads:

When a GPIO pad is configured for cross triggering, the I/O pad assumes the role of one of these four cross trigger signals, and the pad controls and I/O data signals are connected to the associated CTP.

The logical structure of a CTP module is shown in CTP module structure in the Cross-Trigger Port architecture.

Signal names, directions, and pad controls are listed in the CTP Signal Interface.

The register interface for each CTP module is described in the CTN Memory Map section below.

The CTM is a crossbar that aggregates and statically routes cross trigger pulses between various sources and sinks. Typical connections to the CTM include Core Logic Analyzers (CLAs) and CTPs, including other miscellaneous devices. The CTM is compatible with CTPs operating in either of the two signaling modes, point-to-point or wire-OR. Typically, each device or logic module connected to the CTM will act as both a source and a sink for cross trigger pulses.

The source selection and destination routing performed by the CTM are shown in CTM routing structure in the Cross-Trigger Matrix architecture.

The CTM is programmed at runtime via firmware or debug transactions. Proper configuration of the CTMs in each chiplet will minimize trigger latency and prevent loops in the SiP cross trigger network. Configuration is accomplished via CSRs. The CTM register interface is described in the CTN Memory Map section below, and the Programmer’s Guide gives the order in which to program the CTPs and the CTM.

The CTN provides a unified CSR address space accessed via a single AXI-Lite subordinate port. An internal AXI-Lite crossbar (axi_lite_xbar) routes transactions to the CTM and external CTPs based on address decoding. The crossbar registers all five channels at the subordinate port, so no combinational path runs from the port’s inputs to its outputs, and each channel adds one cycle of latency. Each channel’s register holds up to two beats and keeps its READY high while it holds fewer than two. The crossbar serves one CSR access at a time, so the port can accept a second request on a channel while the crossbar is still serving the first.

Table 1 lists the CTM and external-CTP address ranges.

The table shows the default 16 external CTPs. External CTP n occupies the 16 bytes from 0x200 + 0x10*n.

The crossbar is configured with MaxMstTrans=1 and MaxSlvTrans=1, serializing all CSR accesses. This simplification reduces arbitration logic at the cost of concurrent access capability.

The CTN instantiates NUM_CTP external CTPs, 16 by default, using the full cross_trigger_port module with CSR interface, and NUM_INT_CT internal CTPs, 10 by default, using only the cross_trigger_port_core module without registers.

Table 2 compares the modules, configuration, and connections used for external and internal CTPs.

External Cross Trigger Flow

Internal Cross Trigger Flow

The ctn_clock_stop_ctrl module aggregates clock stop requests from multiple sources using a two-stage OR-tree architecture. The module separates CLA-only status from the combined functional halt signal to support independent JTAG visibility and chiplet clock gating control. The CTN sizes its request input with its own NUM_CLK_STOP_REQ parameter, which defaults to 9.

The parameters and ports of ctn_clock_stop_ctrl are listed in ctn_clock_stop_ctrl.

The aggregation logic operates as follows:

The synchronizer resolves the asynchronous JTAG and CLA requests into clk_i, and the output register keeps glitches out of the chiplet’s functional clock gating logic. The combinatorial cla_clock_stop_o output provides immediate visibility of CLA activity to the JTAG interface, allowing debuggers to distinguish between JTAG-initiated and CLA-initiated clock stops.

Table 5 maps CTM port indices to external CTPs, internal CTPs, and clock-stop connections.

Where N = NUM_CTP and M = NUM_INT_CT. This indexing is used for CTM ct_dst_i and ct_src_o port assignment and CTM routing configuration registers.

For the module diagram and signalling modes, see CTN Architecture.

Each CTP is built on cross_trigger_port_core. Its operating mode resets to wire-OR: the CSR MODE field of an external CTP resets to 0, which selects wire-OR, and 1 selects peer-to-peer. INT_CT_MODE sets the mode of each internal CTP.

The parameters and ports of cross_trigger_port_core are listed in cross_trigger_port_core.

The CTM has the following data ports and logical structure:

The parameters and ports of cross_trigger_network are listed in cross_trigger_network.

The CTN depends on the following components:

The Cross Trigger Network combines the Cross Trigger Matrix (CTM) and Cross Trigger Port (CTP) registers into a unified address space. Its generated map keeps the CTP instance count and stride with the allocated apertures:

The CTN adds no CTN-specific registers; it decodes the AXI-Lite CSR interface onto the CTM and CTP blocks it instantiates. The composite SystemRDL top is the common source for these addresses and for the generated RTL constants.

The last two columns state how the network answers a 32-bit access that no register backs, as seen at its AXI-Lite CSR port, and Decode Response Codes defines them and their codes. An address above 0x2FF matches no block and answers DECERR, with read data 0xBADCAB1E.