eFuse

In this chapter, eFuse and OTP are used interchangeably.

1. Overview

The eFuse IP provides secure One-Time Programmable (OTP) memory access for the OCAH system. A foundry-agnostic controller caches the array into shadow registers at boot, then exposes program and read operations over AXI4-Lite with layered hardware and software locks. Foundry-specific timing and macro signaling sit behind a replaceable SHIM so the software interface stays the same across OTP technologies.

2. Description and Features

Boot-time fuse sense: An automatic bulk read loads the full OTP array into shadow registers so later CSR access is not bound to OTP timing.
Dual AXI4-Lite paths: SMC is the functional access path; JTAG is the debug path, with lifecycle-dependent restrictions.
Lifecycle and token gating: SEP instances further restrict access by lifecycle state, secure test mode, and RMA or security-disable tokens.

3. Architecture

The eFuse IP provides secure One-Time Programmable (OTP) memory management with foundry-agnostic design. The layered architecture separates security control logic from foundry-specific implementation details, enabling deployment across different OTP technologies while maintaining consistent security characteristics and software interfaces.

3.1. Interface Controller

The eFuse Interface Controller (efuse_interface_controller.sv) provides dual-path access control with security policy enforcement.

3.2. Access Paths

SMC AXI4-Lite Interface: Functional access for normal system operations
JTAG AXI4-Lite Interface: Debug access for manufacturing test and development

3.3. Command-path ownership

After fuse sense completes, software program and read requests share one command path to the OTP bank. EFUSE_PROGRAM_CTRL.program_enable takes that path in preference to EFUSE_READ_CTRL.read_enable, so the two enables must be asserted exclusively; a read issued while program_enable is set does not reach the bank. The program and read sequences are in the eFuse section of the Programmer’s Guide.

3.4. Destination Endpoints

Table 1 identifies the consumers of sensed fuse data.

Table 1. eFuse destination endpoints
Endpoint	Description
Shadow Registers	High-performance boot-time caching for rapid access without OTP timing constraints
eFuse CSR	Control and status registers for read, program, and verification operations
MMR	Memory-Mapped Registers for SEP security tokens with specialized access control
Interface SHIM CSR	Configuration registers for foundry-specific timing adaptation. Implemented by the adopter, but always accessed via the interface controller.

3.5. Shadow Register Subsystem

The shadow register subsystem accelerates OTP access by caching eFuse contents at boot time. On power-up, a dedicated FSM automatically issues a bulk read command (with access_length_words set to cover the full eFuse bank), copying all OTP data into the shadow registers. This ensures the shadow registers are fully populated and always synchronized with the OTP state at each boot.

3.6. Features

Table 2 summarises the shadow-register capacity and access features.

Table 2. eFuse shadow-register features
Feature	Description
Capacity	Configurable (default: 8192 bits / 1KB, 256 × 32-bit words), set via the `SHADOW_REG_BITS` parameter
Initialization	Automatic boot-time loading via Fuse Sense FSM
Access Control	Multi-tier hardware and software lock mechanisms
Data Consistency	Maintains synchronization with underlying OTP storage upon each power-on reset

3.7. State Machine Architecture

The read interface FSM (efuse_read_interface.sv) operates in a simple two-state sequence, transitioning from idle to waiting for a response as it handles on-demand eFuse reads that fall outside the shadow register cache. This mechanism works alongside the shadow subsystem, providing direct access only when necessary, and actively reports status to support robust error handling and retry logic.

The program interface FSM (efuse_program_interface.sv) enforces the write-once nature of OTP hardware, ensuring that programmed data cannot be altered once set. It supports write-and-verify procedures for reliability, integrating verification steps that check programmed values against intended data, and fully blocks any unauthorized overwrites to maintain data integrity.

Readback Capture Behavior:

When a read command completes successfully, the read interface captures data from the SHIM response into the read-data CSR during the ST_WAIT_RESP state. This data is retained and continues to be available after the FSM returns to idle, allowing software to retrieve the result without a re-read.

3.8. Parameterized Command Typedefs

The fuse command request/response structs exchanged between the controller and the SHIM are not declared with fixed types. Instead, they are generated from parameterized preprocessor macros defined in efuse_typedef.svh. This keeps the command interface technology-agnostic: each integration supplies its own address, data, access-length, and command types, while the macros guarantee a consistent struct layout and field ordering across all OTP variants.

Table 3 relates each command macro to its generated type and purpose.

Table 3. eFuse command type macros
Macro	Generated Type	Purpose
`EFUSE_COMMAND_REQ_T`	`fuse_command_req_t`	Controller-to-SHIM command request
`EFUSE_COMMAND_RESP_T`	`fuse_command_resp_t`	SHIM-to-controller command response

The request macro is parameterized over the struct name plus four payload types (addr_t, data_t, access_length_words_t, command_t), allowing the controller to size the address space, transfer length, and command encoding to match the target OTP technology:

`define EFUSE_COMMAND_REQ_T(fuse_command_req_t, addr_t, data_t, access_length_words_t, command_t)  \
  typedef struct packed {                                       \
    addr_t                    address;             // Target address       \
    logic                     program_data;        // Data to program (1'b1) \
    access_length_words_t     access_length_words; // Transfer size        \
    command_t                 command;             // Command type         \
    logic                     valid;               // Request valid        \
  } fuse_command_req_t;

The response macro is parameterized over the struct name and the data_t read-data type:

`define EFUSE_COMMAND_RESP_T(fuse_command_resp_t, data_t)       \
  typedef struct packed {                                       \
    data_t              data;       // Read data                \
    logic               status;     // Operation status         \
    logic               valid;      // Response valid            \
  } fuse_command_resp_t;

A typical instantiation expands both macros with the integration’s local types:

`EFUSE_COMMAND_REQ_T(fuse_command_req_t, addr_t, data_t, access_length_words_t, command_t)
`EFUSE_COMMAND_RESP_T(fuse_command_resp_t, data_t)

3.9. Foundry-Specific Signals

Table 4 compares the signals required by the supported OTP interface variants.

Table 4. Example Hardware Interfaces by OTP Variant
OTP Variant	Hardware Interface Signals
Adopter OTP macro	Adopter-defined macro-side signals
Current Example Model	APB interface with register-based control

3.10. Interface SHIM Layer

The Interface SHIM (efuse_interface_shim.sv) is an example, foundry-specific implementation of the custom fuse command interface. Its role is to translate the controller’s generic commands into the signaling expected by a particular OTP macro; in this reference version the macro-side interface is APB, but a real integration would replace this with the foundry’s native signals.

The SHIM decodes three command types from the controller:

Read — fetch one or more words from the bank.
Program — burn new bits into the bank.
Program/read-back — program, then read back to verify success.

It implements these with dedicated read and program FSMs that sequence the macro-side transactions and return a fuse_command_resp_t to the controller. Foundry-specific timing and configuration (for example, program pulse widths) are exposed through the SHIM Control CSRs, accessed over the fuse_bank_ctrl AXI4-Lite interface.

3.11. eFuse Bank Model

The eFuse bank model (efuse_bank_model.sv) is a reference, simulation-only stand-in for the real foundry OTP macro. It is a 3KB (768 x 32-bit word) store fronted by a standard APB interface, and it emulates the set-once behavior of real OTP so the controller and SHIM can be exercised end-to-end without silicon. In a production integration it is replaced by the actual foundry macro driven by the SHIM.

3.12. Access Permissions and Security

Access control is layered for defense in depth: per-field permissions are described by efuse_field_map_i, lock state is enforced by the eFuse guard (efuse_guard.sv), security-disable tokens are validated, and access can additionally be gated by the chip lifecycle state.

Each eFuse field is described by a rule_t entry that pairs an address range with a 4-bit lock permission field:

typedef struct packed {
    logic [EfuseFieldMapIdxWidth-1:0] idx;        // Field index
    logic [3:0]                           lock;       // Permission bits
    logic [31:0]                          start_addr; // Field start address
    logic [31:0]                          end_addr;   // Field end address
} rule_t;

The lock field encodes read, write, and secure-test-mode permissions for the field (Table 5).

Table 5. eFuse lock-field encoding
Bits	Function	Encoding
`lock[0]`	Read	`0` = readable, `1` = read-locked
`lock[2:1]`	Write	`00` = unlocked, `10` = set-only (1’s may be added, never cleared), `11` = write-locked
`lock[3]`	Secure-test write lock	`1` adds a shadow write lock while secure test mode is active; `0` adds no such lock. Other locks still apply.

3.13. Hardware vs. Software Locks

The same permission semantics are reached through two independent mechanisms, and the guard enforces whichever is more restrictive (Table 6).

Table 6. eFuse hardware and software locks
Property	Hardware Lock	Software Lock
Source	Permission bits fused into the eFuse array (the field map reflects the programmed values)	Runtime writes to the `LOCKS` CSR (write-1-to-set)
Persistence	Permanent — backed by one-time-programmable bits and cannot be cleared once set	Volatile — retained only until the next system reset
Reversibility	Irreversible by any means	Cleared by reset, allowing the field to be re-opened
Typical use	Final production lockdown of provisioned secrets	Temporary protection during boot, debug, or staged provisioning

Because software locks are write-1-to-set, firmware can tighten access at runtime but can never loosen a restriction without a reset; hardware locks cannot be loosened at all. On top of these per-field locks, sensitive fields can be further gated by the chip lifecycle state and by secure test mode (lock[3]), so a field may be accessible in one operational mode and fully blocked in another even when its read/write bits are clear.

For sensitive functions, such as those governed by the MMR registers, the system enforces token-based security. Only by providing the correct 256-bit tokens, such as the RMA SOP Token for state transitions, the RMA Chiplet Token for chiplet-specific operations, or the Security Disable Token to override protections, can access to these resources be granted.

3.14. Security Disable Bypass Mechanism

The eFuse interface controller supports a security disable bypass mechanism via the security_disable_i input signal. This mechanism is primarily used for test and debug scenarios where the automatic fuse sensing sequence needs to be bypassed.

Behavior when security_disable_i is asserted:

Table 7 describes the sensing behavior when security_disable_i is asserted.

Table 7. eFuse security-disable behavior
Behavior	Description
FSM Bypass	The automatic fuse sensing state machine is bypassed and does not issue read commands to the physical eFuse bank.
Shadow Register Output	Shadow register values are output directly to downstream logic via `shadow_regs_o`, regardless of `fuse_sense_done` status.
Shadow Register Loading	Shadow registers are not loaded from fuse command responses; they retain their reset values (all zeros for SMC).
APB Access	APB access to shadow registers is permitted without waiting for `fuse_sense_done` completion.
Reset Values	When the system is in reset state with `security_disable_i` asserted, shadow registers are initialized to zero (default reset value for SMC).

For SMC, the internal security disable signal is directly driven by the security_disable_i input port.

3.15. Lifecycle State (LC_STATE) Effects

The eFuse interface controller enforces access restrictions based on the chip’s lifecycle state.

Lifecycle State Encoding:

Table 8 lists the lifecycle encodings used by the eFuse controller.

Table 8. eFuse lifecycle encodings
State	Encoding	Description
TEST_DEV	0x0	Test/Development state (default)
PROD	0x1	Production state
PROD_DBG	0x1 + DEMOTE=1	Production Debug (volatile, clears on reset)
RMA_SOP	0x2, 0x3	RMA System-in-Package
RMA_CHIPLET	0x6-0x7	RMA Chiplet level
PROD_END	0x8	Production End (terminal state)
INVALID	All others	Invalid state (error fallback)

JTAG Access Control Based on LC_STATE:

JTAG access policies differ between SMC and SEP variants. The table below describes the SMC variant policy, which restricts JTAG access in production and RMA states. SEP applies a different policy: in restricted states (PROD or RMA_SIP), JTAG accesses to the MMR (token register) space remain allowed for token programming; accesses outside the MMR space are blocked with an error response.

SMC JTAG Policy:

When lifecycle state is PROD (0x1) or RMA_SOP (0x2, 0x3), JTAG access to eFuse registers is restricted (Table 9).

Table 9. eFuse JTAG permissions (SMC)
Access Type	PROD/RMA_SOP State	Other States
JTAG Write	Blocked (error response)	Allowed
JTAG Read	Blocked except JTAG_PUBLIC_IDENTITY	Allowed
JTAG Read JTAG_PUBLIC_IDENTITY	Allowed	Allowed

The access control mechanism uses an AXI-Lite demux that routes blocked requests to an error slave. When a request is blocked, the error slave returns an error response with data value 0xbadcab1e.

SMC exception for JTAG_PUBLIC_IDENTITY:

Even in PROD or RMA_SOP states, JTAG read access to the JTAG_PUBLIC_IDENTITY register is permitted. This allows identification of the chip for manufacturing and field returns without exposing sensitive eFuse contents.

3.16. Secure Test Mode (secure_tm_i)

The eFuse interface controller supports a Secure Test Mode via the secure_tm_i input signal. This mode provides additional protection for sensitive security assets during secure manufacturing test operations.

Behavior when secure_tm_i is asserted:

Table 10 describes the restrictions applied when secure_tm_i is asserted.

Table 10. eFuse secure-test behavior
Behavior	Description
Fuse Command Blocking	All fuse commands to the physical eFuse bank are blocked. The guard logic filters incoming requests and returns default responses.
RMA Token Protection	RMA SOP and RMA Chiplet tokens are disconnected from shadow register outputs (set to zero), preventing token exposure during test.
Write Lock Contribution	Secure test mode contributes to write lock status, preventing shadow register modifications.
Response Behavior	When fuse commands are blocked, default response values (all zeros) are returned to requesters.

SMC Configuration:

For SMC, secure_tm_i is tied to logic 0, meaning Secure Test Mode is not active during normal SMC operation. This signal is primarily relevant for SEP where sensitive RMA tokens must be protected during manufacturing test flows.

4. Interface

4.1. Configuration Parameters

The OTP has a total storage capacity of 1 KB, organized as 256 words of 32 bits.

The parameters and ports of efuse_interface_controller are listed in efuse_interface_controller.

4.2. Main AXI4-Lite Interfaces

The eFuse controller provides two AXI4-Lite interfaces for register access: functional access from the SMC and debug access from JTAG.

4.3. Fuse Bank Control Interface

AXI4-Lite interface to the fuse bank control registers in the SHIM, carried on fuse_bank_ctrl_req_o and fuse_bank_ctrl_resp_i of types efuse_axil_req_t and efuse_axil_resp_t. The controller forwards accesses outside its own address windows on this interface.

4.4. Fuse Command Interface

Custom interface for SHIM state machine communication.

4.5. Security and Control Signals

The controller has no lifecycle-state input port. When HAS_LC_STATE is set, it takes the lifecycle state from the fuses: during fuse sensing it loads the low LC_STATE_WIDTH bits of shadow word efuse_pkg::ShadowIdxLcState and stores them differentially encoded in the shadow map. The shadow word index is fixed in efuse_pkg. LC_STATE_BIT_POSITION is used only by the guard, which derives the RMA SiP and chiplet token bit addresses from it as LC_STATE_BIT_POSITION + 1 and LC_STATE_BIT_POSITION + 2.

4.6. Fuse Command Protocol

Custom command interface between controller and SHIM:

Request Structure (fuse_command_req_t):

typedef struct packed {
    addr_t                    address;           // Target address in bits
    logic                     program_data;      // Data to program (1'b1)
    access_length_words_t     access_length_words; // Transfer size
    command_t                 command;           // Command type
    logic                     valid;             // Request valid
} fuse_command_req_t;

Response Structure (fuse_command_resp_t):

typedef struct packed {
    data_t              data;       // Read data
    logic               status;     // Operation status
    logic               valid;      // Response valid
} fuse_command_resp_t;

Command Types:

FUSE_COMMAND_READ (2’b00): Read operation
FUSE_COMMAND_PROGRAM (2’b01): Program operation
FUSE_COMMAND_PROGRAM_READ_BACK (2’b10): Program with verification

5. Memory Map and Register Reference

5.1. Memory Map

eFuse is not one universally placed address space. SEP, SMC, and the Key Manager pass-through expose different subsets and placements. The generated tables below compose those integration-specific views from their canonical SystemRDL roots.

Table 11. SEP eFuse Placement
Base Address	End Address	Size	Decoded Extent	Unit	Description
0x10930000	0x109303FF	1 KiB	1 KiB	Shadow Registers	Cached eFuse shadow registers.
0x10930400	0x109304FF	256 B	28 B	eFuse Control CSR	eFuse command and status registers.
0x10930500	0x109305FF	256 B	116 B	MMR Registers	eFuse security-token registers.

Table 12. SMC eFuse Placement
Address Range	Size	Decoded Extent	Unit	Description
BASE + 0x7000 – BASE + 0x7FFF	4 KiB	1 KiB	Shadow Registers	Address map for efuse shadow registers providing access to various chip configuration and ID fields
BASE + 0x8000 – BASE + 0x8FFF	4 KiB	28 B	eFuse Control CSR	eFuse command and status registers.

Table 13. Key Manager eFuse Pass-Through
Base Address	End Address	Size	Decoded Extent	Unit	Description
0x00011000	0x000113FF	1 KiB	1 KiB	Shadow Registers	SEP eFuse shadow-register pass-through.
0x00011400	0x000114FF	256 B	28 B	eFuse Control CSR	SEP eFuse command and status pass-through.
0x00011500	0x000115FF	256 B	116 B	MMR Registers	SEP eFuse security-token pass-through.

At the IP boundary, each region’s base address and aperture size are integration parameters; the generated tables show the selected integration values. The MMR region exists only when the eFuse instance includes lifecycle state (HAS_LC_STATE=1).

5.2. Detailed Register Map

5.2.1. Shadow Registers

The shadow registers provide cached read access to eFuse contents, loaded automatically from the physical eFuse array during boot. The field layout is defined by the SystemRDL sources of the instantiating subsystem; the generated table below is authoritative for addresses, widths, and access rights of the instance documented in this section.

Efuse address map of physical efuse macro

Address map for efuse shadow registers providing access to various chip configuration and ID fields

Register Arrays:

I2C_I3C_ID[9]: 9 registers, base 0x28, stride 0x8
SPARE[28]: 28 registers, base 0x80, stride 0x20

Register List:

Table 14. Efuse address map of physical efuse macro register list
Address	Name	Access	Description
0x0	LOCKS	RW	Lock controls for each fuse field. When write locked, the corresponding field is not programmable. When read locked, the shadow register is not readable.
0x8	JTAG_PUBLIC_IDENTITY	RW	JTAG-public exception window. In PROD and RMA_SiP, JTAG reads of this range are admitted while JTAG access to every other fuse field is blocked. Encoding is adopter-defined; the harness does not interpret or consume the value. The slot-0 read lock still hides the bits when set.
0x28 - 0x68	I2C_I3C_ID[9]	RW	I2C/I3C interface ID
0x70	SMC_CONFIG	RW	SMC boot and configuration controls sourced from fuse. Only the low word carries assigned bits, so firmware reads it as a single 32-bit access.
0x78	OCCP_TRANSPORT_TIMEOUT	RW	OCCP transport timeout in the low word; upper word reserved.
0x80 - 0x3E0	SPARE[28]	RW	Individually lockable 256-bit spare region, reserved for fields assigned after the RTL is frozen. Each element has its own write/read lock pair in LOCKS.

Register Details:

LOCKS

Table 15. smc_efuse_map.LOCKS fields
Bits	Field	Access	Reset	Description
63	spare27_read_lock	RW1S	0x0	Spare 27 read lock (slot 31). When set, SPARE[27] is not readable.
62	spare27_write_lock	RW1S	0x0	Spare 27 write lock (slot 31). When set, SPARE[27] is not writable.
61	spare26_read_lock	RW1S	0x0	Spare 26 read lock (slot 30). When set, SPARE[26] is not readable.
60	spare26_write_lock	RW1S	0x0	Spare 26 write lock (slot 30). When set, SPARE[26] is not writable.
59	spare25_read_lock	RW1S	0x0	Spare 25 read lock (slot 29). When set, SPARE[25] is not readable.
58	spare25_write_lock	RW1S	0x0	Spare 25 write lock (slot 29). When set, SPARE[25] is not writable.
57	spare24_read_lock	RW1S	0x0	Spare 24 read lock (slot 28). When set, SPARE[24] is not readable.
56	spare24_write_lock	RW1S	0x0	Spare 24 write lock (slot 28). When set, SPARE[24] is not writable.
55	spare23_read_lock	RW1S	0x0	Spare 23 read lock (slot 27). When set, SPARE[23] is not readable.
54	spare23_write_lock	RW1S	0x0	Spare 23 write lock (slot 27). When set, SPARE[23] is not writable.
53	spare22_read_lock	RW1S	0x0	Spare 22 read lock (slot 26). When set, SPARE[22] is not readable.
52	spare22_write_lock	RW1S	0x0	Spare 22 write lock (slot 26). When set, SPARE[22] is not writable.
51	spare21_read_lock	RW1S	0x0	Spare 21 read lock (slot 25). When set, SPARE[21] is not readable.
50	spare21_write_lock	RW1S	0x0	Spare 21 write lock (slot 25). When set, SPARE[21] is not writable.
49	spare20_read_lock	RW1S	0x0	Spare 20 read lock (slot 24). When set, SPARE[20] is not readable.
48	spare20_write_lock	RW1S	0x0	Spare 20 write lock (slot 24). When set, SPARE[20] is not writable.
47	spare19_read_lock	RW1S	0x0	Spare 19 read lock (slot 23). When set, SPARE[19] is not readable.
46	spare19_write_lock	RW1S	0x0	Spare 19 write lock (slot 23). When set, SPARE[19] is not writable.
45	spare18_read_lock	RW1S	0x0	Spare 18 read lock (slot 22). When set, SPARE[18] is not readable.
44	spare18_write_lock	RW1S	0x0	Spare 18 write lock (slot 22). When set, SPARE[18] is not writable.
43	spare17_read_lock	RW1S	0x0	Spare 17 read lock (slot 21). When set, SPARE[17] is not readable.
42	spare17_write_lock	RW1S	0x0	Spare 17 write lock (slot 21). When set, SPARE[17] is not writable.
41	spare16_read_lock	RW1S	0x0	Spare 16 read lock (slot 20). When set, SPARE[16] is not readable.
40	spare16_write_lock	RW1S	0x0	Spare 16 write lock (slot 20). When set, SPARE[16] is not writable.
39	spare15_read_lock	RW1S	0x0	Spare 15 read lock (slot 19). When set, SPARE[15] is not readable.
38	spare15_write_lock	RW1S	0x0	Spare 15 write lock (slot 19). When set, SPARE[15] is not writable.
37	spare14_read_lock	RW1S	0x0	Spare 14 read lock (slot 18). When set, SPARE[14] is not readable.
36	spare14_write_lock	RW1S	0x0	Spare 14 write lock (slot 18). When set, SPARE[14] is not writable.
35	spare13_read_lock	RW1S	0x0	Spare 13 read lock (slot 17). When set, SPARE[13] is not readable.
34	spare13_write_lock	RW1S	0x0	Spare 13 write lock (slot 17). When set, SPARE[13] is not writable.
33	spare12_read_lock	RW1S	0x0	Spare 12 read lock (slot 16). When set, SPARE[12] is not readable.
32	spare12_write_lock	RW1S	0x0	Spare 12 write lock (slot 16). When set, SPARE[12] is not writable.
31	spare11_read_lock	RW1S	0x0	Spare 11 read lock (slot 15). When set, SPARE[11] is not readable.
30	spare11_write_lock	RW1S	0x0	Spare 11 write lock (slot 15). When set, SPARE[11] is not writable.
29	spare10_read_lock	RW1S	0x0	Spare 10 read lock (slot 14). When set, SPARE[10] is not readable.
28	spare10_write_lock	RW1S	0x0	Spare 10 write lock (slot 14). When set, SPARE[10] is not writable.
27	spare9_read_lock	RW1S	0x0	Spare 9 read lock (slot 13). When set, SPARE[9] is not readable.
26	spare9_write_lock	RW1S	0x0	Spare 9 write lock (slot 13). When set, SPARE[9] is not writable.
25	spare8_read_lock	RW1S	0x0	Spare 8 read lock (slot 12). When set, SPARE[8] is not readable.
24	spare8_write_lock	RW1S	0x0	Spare 8 write lock (slot 12). When set, SPARE[8] is not writable.
23	spare7_read_lock	RW1S	0x0	Spare 7 read lock (slot 11). When set, SPARE[7] is not readable.
22	spare7_write_lock	RW1S	0x0	Spare 7 write lock (slot 11). When set, SPARE[7] is not writable.
21	spare6_read_lock	RW1S	0x0	Spare 6 read lock (slot 10). When set, SPARE[6] is not readable.
20	spare6_write_lock	RW1S	0x0	Spare 6 write lock (slot 10). When set, SPARE[6] is not writable.
19	spare5_read_lock	RW1S	0x0	Spare 5 read lock (slot 9). When set, SPARE[5] is not readable.
18	spare5_write_lock	RW1S	0x0	Spare 5 write lock (slot 9). When set, SPARE[5] is not writable.
17	spare4_read_lock	RW1S	0x0	Spare 4 read lock (slot 8). When set, SPARE[4] is not readable.
16	spare4_write_lock	RW1S	0x0	Spare 4 write lock (slot 8). When set, SPARE[4] is not writable.
15	spare3_read_lock	RW1S	0x0	Spare 3 read lock (slot 7). When set, SPARE[3] is not readable.
14	spare3_write_lock	RW1S	0x0	Spare 3 write lock (slot 7). When set, SPARE[3] is not writable.
13	spare2_read_lock	RW1S	0x0	Spare 2 read lock (slot 6). When set, SPARE[2] is not readable.
12	spare2_write_lock	RW1S	0x0	Spare 2 write lock (slot 6). When set, SPARE[2] is not writable.
11	spare1_read_lock	RW1S	0x0	Spare 1 read lock (slot 5). When set, SPARE[1] is not readable.
10	spare1_write_lock	RW1S	0x0	Spare 1 write lock (slot 5). When set, SPARE[1] is not writable.
9	spare0_read_lock	RW1S	0x0	Spare 0 read lock (slot 4). When set, SPARE[0] is not readable.
8	spare0_write_lock	RW1S	0x0	Spare 0 write lock (slot 4). When set, SPARE[0] is not writable.
7	occp_transport_timeout_read_lock	RW1S	0x0	OCCP transport timeout read lock (slot 3). When set, OCCP_TRANSPORT_TIMEOUT is not readable.
6	occp_transport_timeout_write_lock	RW1S	0x0	OCCP transport timeout write lock (slot 3). When set, OCCP_TRANSPORT_TIMEOUT is not writable.
5	smc_config_read_lock	RW1S	0x0	SMC config read lock (slot 2). When set, SMC_CONFIG is not readable.
4	smc_config_write_lock	RW1S	0x0	SMC config write lock (slot 2). When set, SMC_CONFIG is not writable.
3	i2c_i3c_id_read_lock	RW1S	0x0	I2C/I3C ID read lock (slot 1). When set, no I2C_I3C_ID element is readable.
2	i2c_i3c_id_write_lock	RW1S	0x0	I2C/I3C ID write lock (slot 1). When set, no I2C_I3C_ID element is writable.
1	jtag_public_identity_read_lock	RW1S	0x0	JTAG public identity read lock (slot 0). When set, JTAG_PUBLIC_IDENTITY is not readable.
0	jtag_public_identity_write_lock	RW1S	0x0	JTAG public identity write lock (slot 0). When set, JTAG_PUBLIC_IDENTITY is not writable.

JTAG_PUBLIC_IDENTITY

Table 16. smc_efuse_map.JTAG_PUBLIC_IDENTITY fields
Bits	Field	Access	Reset	Description
255:0	value	RW	0x0	Opaque payload. Encoding is adopter-defined; the harness does not interpret it.

I2C_I3C_ID[9]

Table 17. smc_efuse_map.I2C_I3C_ID[9] fields
Bits	Field	Access	Reset	Description
63:0	interface_id	RW	0x0	I2C or I3C ID configuration: * Static ID mode: [6:0] contains ID, [63:7] reserved * Provisional ID mode: [63:0] full ID

SMC_CONFIG

Table 18. smc_efuse_map.SMC_CONFIG fields
Bits	Field	Access	Reset	Description
63:16	config_rsvd_high	RW	0x0	Reserved for future configuration bits.
15	dft_ignore_error	RW	0x0	When set, boot continues despite a reported memory repair or MBIST failure.
14:8	config_rsvd_mid	RW	0x0	Reserved for future configuration bits.
7	sram_auto_zero_disable	RW	0x0	When set, boot skips the SRAM auto-zero initialisation pass.
6:1	config_rsvd_low	RW	0x0	Reserved for future configuration bits.
0	rom_flip_endianness	RW	0x0	When set, the ROM interface swaps byte order on instruction fetch.

OCCP_TRANSPORT_TIMEOUT

Table 19. smc_efuse_map.OCCP_TRANSPORT_TIMEOUT fields
Bits	Field	Access	Reset	Description
63:32	timeout_rsvd	RW	0x0	Reserved for extension of the timeout encoding.
31:0	timeout	RW	0x0	Transport timeout value consumed by the boot ROM OCCP driver.

SPARE[28]

Table 20. smc_efuse_map.SPARE[28] fields
Bits	Field	Access	Reset	Description
255:0	rsvd	RW	0x0	Spare fuse bits for future use.

5.2.2. MMR Registers

The MMR (Memory Mapped Register) space provides access to security tokens for authentication, including RMA tokens and security disable tokens.

eFuse Token Registers Address Map

Security-token input and match-status registers for RMA and secure-disable eFuse tokens.

Register Arrays:

RMA_SIP_TOKEN_I[8]: 8 registers, base 0x0, stride 0x4
RMA_CHIPLET_TOKEN_I[8]: 8 registers, base 0x20, stride 0x4
SEC_DISABLE_TOKEN_I[8]: 8 registers, base 0x40, stride 0x4

Register List:

Table 21. eFuse Token Registers Address Map register list
Address	Name	Access	Description
0x0 - 0x1C	RMA_SIP_TOKEN_I[8]	RW	Software-writeable RMA token word. The assembled token is hashed and compared against the fused value to authorize lifecycle (LC) state transitions.
0x20 - 0x3C	RMA_CHIPLET_TOKEN_I[8]	RW	Software-writeable RMA token word. The assembled token is hashed and compared against the fused value to authorize lifecycle (LC) state transitions.
0x40 - 0x5C	SEC_DISABLE_TOKEN_I[8]	RW	Software-writeable security-disable token word. The assembled token is hashed and compared against the post-silicon injected value to authorize security_disable.
0x60	TOKEN_EOP	W	Token end-of-packet control. Writing the per-token go bit signals that all token words have been written and triggers a pulse to begin token hashing.
0x64	RMA_SIP_TOKEN_MATCH	R	Token match status. Reports the result of the token hash comparison (match, mismatch, or error).
0x68	RMA_CHIPLET_TOKEN_MATCH	R	Token match status. Reports the result of the token hash comparison (match, mismatch, or error).
0x6C	SEC_DISABLE_TOKEN_MATCH	R	Token match status. Reports the result of the token hash comparison (match, mismatch, or error).
0x70	TOKEN_MATCH_FAULT	R	Token comparator redundancy fault status. The token match logic is triple redundant and is not a majority vote: all three comparators must agree and each must drive a legal differential pair. A bit sets when the comparators for that token disagree, which may indicate a fault injection or FIB attack. The corresponding token_match_status then reads the error code 6'b111111 and an interrupt is raised to the SEP CPU. Bits are sticky until reset.

Register Details:

RMA_SIP_TOKEN_I[8]

Table 22. efuse_mmr.RMA_SIP_TOKEN_I[8] fields
Bits	Field	Access	Reset	Description
31:0	token	RW	-	Portion of writeable version of RMA_*_TOKEN, hashed, and compared with fused value to allow LC to change states.

RMA_CHIPLET_TOKEN_I[8]

Table 23. efuse_mmr.RMA_CHIPLET_TOKEN_I[8] fields
Bits	Field	Access	Reset	Description
31:0	token	RW	-	Portion of writeable version of RMA_*_TOKEN, hashed, and compared with fused value to allow LC to change states.

SEC_DISABLE_TOKEN_I[8]

Table 24. efuse_mmr.SEC_DISABLE_TOKEN_I[8] fields
Bits	Field	Access	Reset	Description
31:0	token	RW	-	Portion of writeable version of SEC_DISABLE_TOKEN, hashed, and compared with the post silicon injected values to allow security_disable.

TOKEN_EOP

Table 25. efuse_mmr.TOKEN_EOP fields
Bits	Field	Access	Reset	Description
31:17	Reserved	-	-	Reserved
16	secure_disable_token_go	W 1P	0x0	Write 1 to indicate that all token data has been written; this generates a pulse to begin token hashing.
15:9	Reserved	-	-	Reserved
8	rma_chiplet_token_go	W 1P	0x0	Write 1 to indicate that all token data has been written; this generates a pulse to begin token hashing.
7:1	Reserved	-	-	Reserved
0	rma_sip_token_go	W 1P	0x0	Write 1 to indicate that all token data has been written; this generates a pulse to begin token hashing.

RMA_SIP_TOKEN_MATCH

Table 26. efuse_mmr.RMA_SIP_TOKEN_MATCH fields
Bits	Field	Access	Reset	Description
31:6	Reserved	-	-	Reserved
5:0	token_match_status	R	0x0	Store the status of the token match. Match = 6'b010101, Mismatch = 6'b101010, Error = 6'b111111

RMA_CHIPLET_TOKEN_MATCH

Table 27. efuse_mmr.RMA_CHIPLET_TOKEN_MATCH fields
Bits	Field	Access	Reset	Description
31:6	Reserved	-	-	Reserved
5:0	token_match_status	R	0x0	Store the status of the token match. Match = 6'b010101, Mismatch = 6'b101010, Error = 6'b111111

SEC_DISABLE_TOKEN_MATCH

Table 28. efuse_mmr.SEC_DISABLE_TOKEN_MATCH fields
Bits	Field	Access	Reset	Description
31:6	Reserved	-	-	Reserved
5:0	token_match_status	R	0x0	Store the status of the token match. Match = 6'b010101, Mismatch = 6'b101010, Error = 6'b111111

TOKEN_MATCH_FAULT

Table 29. efuse_mmr.TOKEN_MATCH_FAULT fields
Bits	Field	Access	Reset	Description
31:17	Reserved	-	-	Reserved
16	secure_disable_token_fault	R	0x0	A redundancy fault was detected in the SEC_DISABLE_TOKEN comparators.
15:9	Reserved	-	-	Reserved
8	rma_chiplet_token_fault	R	0x0	A redundancy fault was detected in the RMA_CHIPLET_TOKEN comparators.
7:1	Reserved	-	-	Reserved
0	rma_sip_token_fault	R	0x0	A redundancy fault was detected in the RMA_SIP_TOKEN comparators.

5.2.3. eFuse Control Registers

The eFuse Control CSR provides command and status registers for read, write, and verification operations on the eFuse array. program_enable and read_enable are mutually exclusive. The eFuse command-path ownership rules in the Programmer’s Guide give the order software follows.

eFuse Interface Control Address Map

Program and read command, address, data, status, and timeout registers for the eFuse interface.

Register List:

Table 30. eFuse Interface Control Address Map register list
Address	Name	Access	Description
0x0	EFUSE_INTERFACE_CTRL_STATUS	RW	eFuse interface status and error-clear register. Reports the sense-done flag and request/address error conditions, and provides write-1 strobes to clear those errors.
0x4	EFUSE_PROGRAM_CTRL	RW	eFuse program control and status. Configures the program address and data, triggers a program (optionally with read-back), and reports program progress and completion status.
0x8	EFUSE_READ_CTRL	RW	eFuse read control and status. Configures the read address, triggers a read, and reports read progress and completion status.
0xC	EFUSE_PROGRAM_INTERFACE_READ_DATA	R	Read data captured through the program interface. Hardware debug only; valid only while the program interface state machine is in its capture-data state.
0x10	EFUSE_READ_INTERFACE_READ_DATA	R	Read data returned through the eFuse read interface.
0x14	EFUSE_READ_REQ_TIMEOUT	RW	Read interface timeout configuration. Sets the number of cycles the read interface waits for a SHIM response and enables the read timeout.
0x18	EFUSE_PROGRAM_REQ_TIMEOUT	RW	Program interface timeout configuration. Sets the number of cycles the program interface waits for a SHIM response and enables the program timeout.

Register Details:

EFUSE_INTERFACE_CTRL_STATUS

Table 31. efuse_interface_ctrl.EFUSE_INTERFACE_CTRL_STATUS fields
Bits	Field	Access	Reset	Description
31:11	Reserved	-	-	Reserved
10	efuse_read_addr_error_clear	W 1P	0x0	Clears the read out of bounds error bit (efuse_read_addr_error) in efuse_ctrl_status
9	efuse_program_addr_error_clear	W 1P	0x0	Clears the program out of bounds error bit (efuse_program_addr_error) in efuse_ctrl_status
8	efuse_req_error_clear	W 1P	0x0	Clears the blocked request error bit in efuse_ctrl_status
7	Reserved	-	-	Reserved
6	efuse_read_addr_error	R	0x0	Indicates that an invalid eFuse read address was used (address exceeds the implemented eFuse size). The error must be cleared by writing 1 to efuse_read_addr_error_clear.
5	efuse_program_addr_error	R	0x0	Indicates that an invalid eFuse program address was used (address exceeds the implemented eFuse size). The error must be cleared by writing 1 to efuse_program_addr_error_clear.
4	efuse_req_error	R	0x0	Indicates that the eFuse was blocked because of either read or a program lock. The error must be cleared by writing 1 to efuse_req_error_clear to this register
3:1	Reserved	-	-	Reserved
0	efuse_sense_done	R	-	Indicates if the eFuse state machine has completed

EFUSE_PROGRAM_CTRL

Table 32. efuse_interface_ctrl.EFUSE_PROGRAM_CTRL fields
Bits	Field	Access	Reset	Description
31:28	Reserved	-	-	Reserved
27	program_enable	RW	0x0	When set, enables the program request
26	program_status	R	0x0	0: No Error. 1: Error
25	program_done	R	0x0	When set, the program has completed, the status of which is in program_status
24	program_busy	R	0x0	When set, the program is in progress
23:19	Reserved	-	-	Reserved
18	efuse_program_read_back	RW	0x0	When set, trigger a read back after a program
17	efuse_program_go	RW 1P	0x0	When set, triggers a program to the eFuse. This will be ignored if the lock bit is set
16	efuse_data	RW	0x0	Data to program to eFuse. If this bit is 0, the program request will be ignored
15:0	efuse_addr	RW	0x0	Bit address to program

EFUSE_READ_CTRL

Table 33. efuse_interface_ctrl.EFUSE_READ_CTRL fields
Bits	Field	Access	Reset	Description
31:29	Reserved	-	-	Reserved
28	read_enable	RW	0x0	When set, enables the read request
27	Reserved	-	-	Reserved
26	read_status	R	0x0	0: No Error. 1: Error. Set when read_go is asserted while read is not enabled, the address is out of bounds, or the read request times out.
25	read_done	R	0x0	When set, the read has completed, the status of which is in read_status
24	read_busy	R	0x0	When set, the read is in progress
23:17	Reserved	-	-	Reserved
16	efuse_read_go	RW 1P	0x0	When set, triggers a read to efuse.
15:0	efuse_addr	RW	0x0	Bit address to read

EFUSE_PROGRAM_INTERFACE_READ_DATA

Table 34. efuse_interface_ctrl.EFUSE_PROGRAM_INTERFACE_READ_DATA fields
Bits	Field	Access	Reset	Description
31:0	dout	R	0x0	Read Data from eFuse through program interface. This field is only valid when the efuse programming interface is utilized to burn the efuse IP and only when the state machine is during ST_CAPTUER_DATA state. Hardware debug only

EFUSE_READ_INTERFACE_READ_DATA

Table 35. efuse_interface_ctrl.EFUSE_READ_INTERFACE_READ_DATA fields
Bits	Field	Access	Reset	Description
31:0	dout	R	0x0	Read Data from eFuse through READ interface.

EFUSE_READ_REQ_TIMEOUT

Table 36. efuse_interface_ctrl.EFUSE_READ_REQ_TIMEOUT fields
Bits	Field	Access	Reset	Description
31:29	Reserved	-	-	Reserved
28	read_req_timout_enable	RW	0x0	Enable timeout on read interface
27:0	read_req_timeout_cycles	RW	0x800000	Number of cycles the read interface will wait for a response from the shim. At 100MHz this can count ~= 2.5 seconds.

EFUSE_PROGRAM_REQ_TIMEOUT

Table 37. efuse_interface_ctrl.EFUSE_PROGRAM_REQ_TIMEOUT fields
Bits	Field	Access	Reset	Description
31:29	Reserved	-	-	Reserved
28	program_req_timeout_enable	RW	0x0	Enable timeout on program interface.
27:0	program_req_timeout_cycles	RW	0x800000	Number of cycles the program interface will wait for a response from the shim. At 100MHz this can count ~= 2.5 seconds.

5.2.4. SHIM Control Registers

The SHIM Control CSR provides foundry-specific configuration registers for timing adaptation and eFuse bank initialization. Its placement is adopter-defined within the adopter-owned SMC external aperture; it therefore does not appear at a fixed address in the generated OCAH map.

eFuse SHIM Control Model Address Map

DV model of the eFuse SHIM control interface.

Register List:

Table 38. eFuse SHIM Control Model Address Map register list
Address	Name	Access	Description
0x0	EFUSE_BANK_INIT_TIME	RW	eFuse bank initialization time. Number of cycles to wait for the OTP macro to initialize before sensing can begin.

Register Details:

EFUSE_BANK_INIT_TIME

Table 39. efuse_shim_ctrl.EFUSE_BANK_INIT_TIME fields
Bits	Field	Access	Reset	Description
31:0	init_time	RW	0x20	Most OTP have a initialization time before sensing can be done