AVSBus Controller

Software queues commands by writing AVS_CMD, which pushes a 32-bit word into the command FIFO. The protocol FSM pops each command, prepends the fixed preamble, appends a calculated CRC-3, and shifts the resulting 32-bit subframe out on avs_mdata_o. The target’s reply arrives one subframe later: it is shifted in from avs_sdata_i during the 32 cycles that carry the next command, checked for a valid frame bit and a good CRC, and pushed into the readback FIFO.

Retries are automatic. A slave acknowledgment of 1 (resource unavailable) or 2 (bad CRC) causes the master to resend the command, up to AVS_CFG_0.MAX_RETRIES times after the original attempt. If the last retry also fails, the failing response is delivered to software and MAX_RETRIES_ATTEMPTED_INT is raised. Setting MAX_RETRIES to 0 suppresses both the retries and that interrupt; the failing response is delivered to software instead. A reply whose frame valid bit is set means the target did not respond at all and raises SLAVE_UNRESPONSIVE_INT. There is no separate programmable response timeout.

The master also issues periodic slave resync operations. The FSM stays in AVS_SLAVE_RESYNC for 35 avs_clk cycles, while its resync counter runs from 0 to 34, and holds avs_mdata_o high throughout. avs_mdata_o is also high in the cycles around that state, through idle or the receive half of a retry beforehand and through the launch cycle afterwards, so the high period on the pin is longer than the resync state itself.

AVS_CFG_0.RESYNC_INTERVAL is the number of clk_reg_i cycles the register domain counts, from when it observes the end of the previous resync, before it requests the next one. AVS_CFG_1.FORCE_SLAVE_RESYNC_OPERATION requests one immediately. Either request is registered in the clk_reg_i domain and crosses into the AVS domain through a three-stage avs_clk synchronizer. The master stops launching new commands once it sees the request, and starts the resync from idle after the frame in flight and its reply complete.

Table 1 identifies the register, reference, and generated AVS clocks.

The selected source passes through an anti-glitch mux and then a programmable divider, whose ratio and duty cycle are both 8-bit values in AVS_CFG_1. Out of reset the controller runs on clk_ref_i divided by 4 at a 50% duty cycle. Both divider fields reset to 0, which is a sentinel: the divider keeps its hardware defaults until software writes a non-zero value.

Changing the clock configuration is not glitch-free on its own. Set AVS_CFG_1.TURN_OFF_ALL_PREMUX_CLOCKS to gate both source clocks before changing the source selection or the divider settings, then clear it afterwards.

Power is saved at two levels: AVS_CFG_1.STOP_AVS_CLOCK_ON_IDLE gates the AVS clock whenever the bus is idle, and TURN_OFF_ALL_PREMUX_CLOCKS gates the clocks entering the mux. Restarting a gated AVS clock always begins with a slave resync.

The avsbus_crc3 module computes a 3-bit CRC combinationally over a 32-bit subframe. Two instances are used. The generate instance is fed the outgoing master subframe with its CRC field zeroed, and its output becomes the three bits shifted out last. The check instance is fed the received slave subframe intact, including the CRC the target sent, and reports a good check when the result is zero. A failed check prevents the subframe from updating AVS_LATEST_SLAVE_SUBFRAME and AVS_SLAVE_STATUS, and the retry logic resends the command.

Table 2 compares the command and readback FIFO roles and operation.

Both are instances of avsbus_async_fifo, which requires a power-of-two depth. Pointers cross between the two clock domains as Gray codes through three-stage synchronizers.

While the readback FIFO is full the master launches no further commands, but replies to commands already launched are still pushed as they arrive. A reply that meets a full FIFO is dropped and raises READBACK_OVERFLOW_INT, so a software reader that stops draining AVS_READBACK stalls new commands and can lose the responses to commands already on the bus.

The controller takes three resets. rst_clk_div_ni resets the programmable clock divider, rst_reg_ni resets the register file and the protocol logic, and rst_ref_ni resets the clk_ref_i leg of the anti-glitch clock mux.

rst_clk_div_ni must be deasserted before rst_reg_ni. The divider has to be producing a clock before the logic it feeds leaves reset, otherwise the AVS clock domain never starts.

Because the divider defaults to divide-by-4 on clk_ref_i and the protocol FSM starts as soon as reset is released, the controller begins issuing slave resync operations without any software configuration. Configuration is therefore a matter of adjusting defaults rather than enabling the block. The AVSBus configuration sequence is in the Programmer’s Guide.

Two domains carry functional logic. The register domain, clocked by clk_reg_i, holds the AXI4-Lite bridge, the register file, the command FIFO write side, the readback FIFO read side and interrupt generation. The AVS domain, clocked by the generated avs_clk, holds the protocol FSM, the shift registers and the CRC engines. avs_clock_o is avs_clk after the idle clock gate, so the FSM keeps running while STOP_AVS_CLOCK_ON_IDLE holds the pin clock stopped.

FIFO pointers cross between the domains as Gray codes. Individual control and status bits cross through prim_sync3 three-stage synchronizers, and pulses through prim_sync3_pulse. The reset synchronizers are six stages deep and take their scan bypass from scan_rst_ni.

cur_state_debug_o exposes the FSM state as a 17-bit one-hot vector, resynchronized to clk_reg_i. The states, in bit order from 0, are (Table 3).

Command transmission and response reception overlap: the reply to a command arrives during the subframe that carries the next command, which is why the mid-subframe states do both at once.

Figure 2 shows the transitions between these states, grouping the 17 states into 11 boxes. Each subframe box stands for a SHIFT state, which holds for the 32 bits of a subframe, and the END state that follows it, where the transition is decided; the three retry boxes pair the six AVS_RETRY_* states the same way. The figure omits the self-loops of states that wait: idle, the resync and each SHIFT state. Resync done means that the resync counter has reached 34. RDY means that a command is waiting, the readback FIFO has room and no resync is due. Stop on idle is AVS_CFG_1.STOP_AVS_CLOCK_ON_IDLE: with it set, a command waiting in idle restarts the AVS clock through a resync instead of launching directly. A retry transition is taken when the received subframe has a bad CRC, a resource-unavailable or bad-CRC acknowledgment, or no response, and MAX_RETRIES is above zero; with MAX_RETRIES at zero the RDY and not-RDY transitions apply instead. A reply that arrives during a retry of the preceding command is held and processed after the retries finish. Every retry sequence ends with a slave resync.

Table 4 describes the controller response to each error condition.

For diagnosis, AVS_NORMAL_STATUS reports bus idle, resync, retry-in-progress and FIFO states; AVS_FIFOS_STATUS reports occupied and vacant slots in both FIFOs; AVS_SLAVE_STATUS and AVS_LATEST_SLAVE_SUBFRAME report the target’s most recent acknowledgment and status response; and cur_state_debug_o exposes the FSM state to the surrounding system.

Both subframes are 32 bits: 29 bits of payload followed by a 3-bit CRC. The master subframe carries a fixed 2’b01 preamble in its two most significant bits; the remaining fields occupy the same bit positions as the AVS_CMD register, so software writes a command in wire order.

Table 5 defines the fields transmitted in a master subframe.

Table 6 lists the command-group-zero data types, resolutions, and access modes.

With command group 1 the command code is manufacturer-specific and Table 7 above does not apply.

A received subframe reaches software by two paths. It is pushed into the readback FIFO and read out of AVS_READBACK, which pops the FIFO, or inspected without popping through AVS_DEBUG_READBACK. Independently of the FIFO, a subframe whose frame valid bit is 0 and whose CRC checks also latches into AVS_LATEST_SLAVE_SUBFRAME and AVS_SLAVE_STATUS, so the current target status is visible without waiting for the FIFO to drain.

The AVS clock is derived from one of two sources, optionally divided, and optionally gated while the bus is idle.

AVS_CFG_1.AVS_CLOCK_SELECT[1:0] selects both the source and whether the divider is used: bit 1 picks the source (0 = clk_reg_i, 1 = clk_ref_i) and bit 0 picks the divider (0 = bypass, 1 = divided). The reset value is 2’b11, so the controller comes up on a divided clk_ref_i.

Figure 3 shows the clock path. Each source passes a clock gate that TURN_OFF_ALL_PREMUX_CLOCKS closes, then the anti-glitch mux u_refclk_apbclk_mux selects one of them, choosing clk_ref_i while in reset. The test mux substitutes clk_test_i in test mode. Inside u_clk_div, the glitch-free post-divider mux selects either the undivided clock or the divider output. The result, avs_clk, clocks the AVS domain and reaches avs_clock_o through u_avs_bus_clkgate, which the protocol FSM closes while the bus is idle if STOP_AVS_CLOCK_ON_IDLE is set. Each mux passes its input 0 when its select is 0. Table 8 lists the four settings.

Table 9 defines the source-selection and divider configuration fields.

Gate the clocks with TURN_OFF_ALL_PREMUX_CLOCKS before changing AVS_CLOCK_SELECT, CLK_DIVIDER_VALUE or CLK_DIVIDER_DUTY_CYCLE_NUMERATOR, then release the gate afterwards.

While test_en_i is high the source and divider-bypass muxes ignore AVS_CLOCK_SELECT, and clk_test_i drives the AVS clock directly.

Table 10 identifies the logic reset by each AVSBus reset input.

rst_clk_div_ni must be deasserted before rst_reg_ni. The divider has to be producing a clock before the logic it feeds leaves reset, otherwise the AVS clock domain never starts.

interrupt_o is a level output, asserted while any AVS_INTERRUPT bit is set and its corresponding AVS_INTERRUPT_MASK bit is clear.

Table 11 maps AVS_INTERRUPT bits to the events that set them.

AVS_INTERRUPT_MASK is a disable mask and every bit resets to 1, so all sources are masked after reset and software must clear a bit to enable that source. Interrupt bits are cleared by writing 1 to the matching bit of AVS_INTERRUPT_CLEAR; those bits self-clear.

AVS_CONFIG.AVS_GPIO_ENABLE drives avs_gpio_enable_o, which enables the pads carrying the AVSBus signals: output enable for the avs_clock and avs_mdata pins and input enable for the avs_sdata pin. It resets to 1, because the protocol FSM begins running as soon as reset is deasserted.

Table 12 summarises the subframe and clock timing.

The resync counts are avs_clk cycles at the protocol FSM’s state register. Pin-level setup, hold and propagation figures are a function of the implementation and are not specified by this IP.

The register port takes the AXI4-Lite structs from avsbus_controller_pkg.

The AVSBus Controller occupies a 128-byte address space (0x00-0x7F) reached through its AXI4-Lite port. The register map holds the command and readback FIFO windows, status registers for monitoring the bus and the target, interrupt status, mask and clear registers, and configuration registers for the clock, the retry budget and the resync interval.